DC motors are commonly employed in many industrial applications due to their various advantages. This study aims to compare the response of the Oustaloup-Recursive-Approximation (ORA) and El-Khazali’s approximation method in controlling a DC motor with a FOPID controller. The two employed methods are used to design the FOPID and approximate. For various fractional orders, many behaviours are presented. A simulation comparison between these methods is performed regarding overshoot, settling time and rise time. © 2022 IEEE.
Blind Watermarking Using DCT and Fractional-Order Lorenz System
This paper presents a new blind watermarking system based on the Discrete Cosine Transform (DCT). The system’s security is increased by encrypting the watermark image using the fractional-order Lorenz system. After converting the cover image to the YCbCr color domain, DCT is applied on the Y channel and embedding of the encrypted watermark is performed in the frequency domain. The fractional-order Lorenz system has more parameters than the integer order system, which increase the length of the system key and make it secure against brute-force attacks. Although blind detection of the watermark is not easy, the proposed algorithm successfully detects the hidden watermark by using statistical properties of the DCT coefficients. Standard imperceptibility and robustness measures are used to evaluate the proposed system, and the results are good. © 2022 IEEE.
On Fractional-order Capacitive Wireless Power Transfer System
Wireless power transfer is becoming an increasingly viable solution for the electrical powering of various electronic gadgets. However, precise outputs are not guaranteed with integer systems, so fractional-order capacitors are vital. This paper studies a four-plate fractional capacitive power transfer system by varying six orders of capacitors between the plates along with the load resistance. A mathematical model based on a 4× 4 mutual fractional capacitance matrix is established for equidistantly placed four identical metal plates. Moreover, the chosen circuit topology is identified and analyzed based on the proposed model. © 2022 IEEE.
A Unified System for Encryption and Multi-Secret Image Sharing Using S-box and CRT
Multi-Secret Image Sharing (MSIS) is used when multiple images need to be shared to multiple participants, but the images can not be recovered without the presence of all shares. In this paper, a unified system for performing encryption and (n,n)-MSIS is proposed. While MSIS is based on the XOR operation, encryption combines the utilization of Chinese Remainder Theorem (CRT), SHA-256, and S-box for improved security. The same designed system is used for the generation of secret shares and the recovery of secret images. In addition, a sensitive system key is designed where three pairwise relatively prime subkeys are automatically generated for utilization in the CRT. The resulting secret shares pass statistical evaluation criteria such as RMSE, correlation, and entropy, and give good results for differential attack measures, and runtime. In addition, the proposed system succeeds in passing the NIST SP-800-22 statistical test suite and key sensitivity measures. © 2022 IEEE.
PRNG Using Primitive Roots of Primes and its Utilization in Chess-based Image Encryption
Recently, number theory has proved its importance in cryptography because of its well-known hard problems. For instance, a primitive root for a prime number shows a special property of uniqueness when raised to different powers mod the prime number. In this paper, a Pseudorandom Number Generator (PRNG) is designed based on this property using a prime number and some of its primitive roots. The PRNG is, first, validated for utilization in cryptography applications using histograms, correlation coefficients, and the National Institute of Standards and Technology (NIST) statistical test suite. Then, the PRNG is utilized in an image encryption system and the system security is tested using statistical measures, differential attack measures, and sensitivity to one-bit change. The results are promising and in the expected good ranges. © 2022 IEEE.
Generic Hardware Realization of K Nearest Neighbors on FPGA
K Nearest Neighbors (KNN) algorithm is a straight-forward yet powerful Machine Learning (ML) tool widely used in classification, clustering, and regression applications. In this work, KNN is applied, with three distance metrics, to classify different datasets, experimentally testing each distance metric effect on the classification performance. A static K is applied for the whole dataset optimally chosen based on a 5-fold cross-validation. A reconfigurable hardware realization on field programmable gate array (FPGA) of each distance metric applying selection sort algorithm is proposed. The FPGA realization reaches a throughput up to 4.44 Gbit/sec while only occupying 1% of the Genesys 2 Kintex-7 board area. The algorithm managed to classify all the tested datasets with above 90% accuracy. © 2022 IEEE.
Registerless Multiplierless YCoCg-R and YCoCg Color Space Converters Hardware Implementation
Multimedia data, e.g., images and videos, are widely used over the internet and on computers. Image processing applications require color space conversion to be able to deal with these types of data more efficiently. This paper investigates three color space conversions and proposes simplified combinational hardware designs and FPGA realizations for RGB to YCoCg-R and YCoCg color spaces encoders and decoders and compares them to their sequential counterparts. The proposed hardware design for the encoders and decoders uses only adders and subtractors without any registers or multipliers. The proposed YCoCg-R converter exhibits better resources utilization compared to implementing the design using shift registers, where it uses 56.3% and 72.1% less LUTs and FFs, respectively. Similarly for the YCoCg color space, the combinational design used 48.1% less LUTs and 67.8% less FFs than its sequential counterpart. © 2022 IEEE.
A Secured Lossless Visual Secret Sharing for Color Images Using Arnold Transform
Nowadays, with the rapid growth in information, a fast and secure method is eagerly needed to share images. (n, n)-Visual Secret Sharing (VSS) is used to share a secret image into n shares, where the secret can only be recovered using all the n shares and the recovery must be fast with low computational complexity. This paper proposes a secured lossless (n, n)-VSS system based on Arnold transform and pixel vectorization suitable to be used with binary, grayscale and color images. Multiple security tests were performed such as entropy, correlation, Mean Squared Error (MSE), National Institute of Standards and Technology (NIST) SP-800-22 statistical suite, and differential attacks, which demonstrate the good security of the proposed system. In addition, the time complexity and runtime of the recovery system indicate good efficiency. © 2022 IEEE.
A Unified FPGA Realization for Fractional-Order Integrator and Differentiator
This paper proposes a generic FPGA realization of an IP core for fractional-order integration and differentiation based on the Grünwald–Letnikov approximation. All fractional-order dependent terms are approximated to simpler relations using curve fitting to enable an efficient hardware realization. Compared to previous works, the proposed design introduces enhancements in the fractional-order range covering both integration and differentiation. An error analysis between software and hardware results is presented for sine, triangle and sawtooth signals. The proposed generic design is realized on XC7A100T FPGA achieving frequency of 9.328 MHz and validated experimentally for a sine input signal on the oscilloscope. The proposed unified generic design is suitable for biomedical signal processing applications. In addition, it can be employed as a laboratory tool for fractional calculus education. © 2022 by the authors. Licensee MDPI, Basel, Switzerland.
CORDIC-Based FPGA Realization of a Spatially Rotating Translational Fractional-Order Multi-Scroll Grid Chaotic System
This paper proposes an algorithm and hardware realization of generalized chaotic systems using fractional calculus and rotation algorithms. Enhanced chaotic properties, flexibility, and controllability are achieved using fractional orders, a multi-scroll grid, a dynamic rotation angle(s) in two- and three-dimensional space, and translational parameters. The rotated system is successfully utilized as a Pseudo-Random Number Generator (PRNG) in an image encryption scheme. It preserves the chaotic dynamics and exhibits continuous chaotic behavior for all values of the rotation angle. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used to implement rotation and the Grünwald–Letnikov (GL) technique is used for solving the fractional-order system. CORDIC enables complete control and dynamic spatial rotation by providing real-time computation of the sine and cosine functions. The proposed hardware architectures are realized on a Field-Programmable Gate Array (FPGA) using the Xilinx ISE 14.7 on Artix 7 XC7A100T kit. The Intellectual-Property (IP)-core-based implementation generates sine and cosine functions with a one-clock-cycle latency and provides a generic framework for rotating any chaotic system given its system of differential equations. The achieved throughputs are (Formula presented.) Mbits/s and (Formula presented.) Mbits/s for two- and three-dimensional rotating chaotic systems, respectively. Because it is amenable to digital realization, the proposed spatially rotating translational fractional-order multi-scroll grid chaotic system can fit various secure communication and motion control applications. © 2022 by the authors.