Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels. © 2022 by the authors. Licensee MDPI, Basel, Switzerland.
CNTFET-based ternary address decoder design
With the end of Moore’s law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power- and time-consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre-decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs. © 2022 John Wiley & Sons Ltd.
Ternary SRAM circuit designs with CNTFETs
Static random-access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. © 2023 John Wiley & Sons Ltd.
CNTFET design of a multiple-port ternary register file
Ternary number system offers higher information processing within the same number of digits when compared to binary systems