This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU
Memristor-based quinary half adder
This paper theorizes the possibilities of generalizing a memristor based ternary adder circuit, to a memristor based multi-valued logic adder
Memristor-based redundant binary adder
This paper introduces a memristor based ternary adder, which is an essential building block for any arithmetic ternary operations