This paper presents two general topologies of fractional order oscillators. They employ Current Feedback Op-Amp (CFOA) and RC networks. Two RC networks are investigated for each presented topology. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are investigated in terms of the fractional order parameters. Numerical simulations and P-Spice simulation results are provided for some cases to validate the theoretical findings. The fractional order parameters increase the design flexibility and controllability which is proved by the provided experimental results. © 2018 IEEE.
Frational Order Inverse Filters Based on CCII Family
This paper proposes two generalized topologies of fractional order inverse filters (FOIF). All possible realizations of each topology are investigated using the second generation current conveyor (CCII) family. Inverse fractional highpass (IFHPF), inverse fractional bandpass (IFBPF), and inverse fractional lowpass (IFLPF) filters are realized using the same topology based on the generalized admittances. Numerical and P-Spice simulation results are presented for selected cases to approve the theoretical findings. The fractional order parameters increase the design flexibility and controllability which is validated experimentally. © 2019 IEEE.
A Universal Fractional-Order Memelement Emulation Circuit
This paper proposes a current-/voltage-controlled universal emulator that can realize any fractional-order memelements (FOME). The proposed emulator consists of second-generation current conveyors (CCII) block, two switches, and a multiplier/divider block. The first switch controls the emulator mode (voltage or current), while, the other controls the type of the emulated FOME. The influence of the fractional-order capacitor (FOC) on the pinched hysteresis loop (PHL) area, is discussed which increases the controllability on the double loop area and the working frequency range. Numerical and PSPICE simulations are presented for selected cases to prove the theoretical findings. © 2019 IEEE.
On Series Connections of Fractional-Order Elements and Memristive Elements
This paper proposes a current-controlled fractional-order memristor emulator based on one active building block. The emulator consists of a multiplication mode current conveyor (MMCC) block with three passive elements. Additionally, the series connection of fractional-order inductor (FOI) and fractional-order capacitor (FOC) with memristive elements in the i-v plane is demonstrated numerically for different cases. Changing the order of the FOC or FOI and its effect on the pinched hysteresis loop area are investigated, which improve the controllability of the double loop area, the location of the pinched point, and the operating frequency range. Numerical, PSPICE simulation results, and experimental verification are investigated for different cases to approve the theoretical findings. Moreover, a sensitivity analysis using Monte Carlo simulations for the tolerance of the discrete components of the memristor emulator is investigated. © 2020 IEEE.
Generalized ?+?-order Filter Based on Single CCII
Different generalized filters topologies are proposed in the fractional-order domain. Three voltage-mode topologies and one current-mode topology are used to realize several types of fractional-order filters by applying different admittances combinations. The proposed topologies are designed using a single second-generation current conveyor (CCII-) and two fractional-order capacitors, which add more degrees of freedom for the design. The generalized Fractional Transfer Function (FTF) for each proposed topology is investigated where the fractional-order low-pass, band-pass, high-pass, and notch filters with ?+?)-order are realized. The Numerical results are provided where the stability analysis is presented for different cases. Also, the PSPICE simulations are presented to prove the theoretical findings of selected cases. © 2020 IEEE.
A Simple BJT Inverse Memristor Emulator and Its Application in Chaotic Oscillators
A generalized inverse memristor emulator is proposed based on two BJT transistors as a diode connected with a first order parallel RC filter. The mathematical model of the circuit is presented where the pinched hysteresis loops (PHLs) with different periodic stimuli are analyzed. The numerical, P-Spice simulations and experimental results are presented indicating that the introduced emulator is a simple voltage-controlled generalized inverse memristor. The results show that the PHLs area is increased with increasing the applied frequency. In addition, the proposed emulator is employed in a simple chaotic circuit. The effect of the inductor’s values on the chaotic system is investigated and the P-Spice simulations are performed to approve the numerical results. © 2019 IEEE.
Fractional-order Memristor Emulator with Multiple Pinched Points
This paper proposes a current-/voltage-controlled universal emulator that can realize any fractional-order memelements (FOME)
A universal floating fractional-order elements/memelements emulator
This paper proposes two generalized topologies of fractional order inverse filters (FOIF)
Fractional-order oscillators based on a single Op-Amp
This chapter introduces a family of fractional-order oscillators based on a single operational amplifier (Op-Amp) with two fractional-order capacitors. Twelve different fractional-order oscillator circuits are investigated where the state matrix, oscillation frequency, and oscillation condition for each circuit are presented. The phase difference between the two oscillatory outputs is deduced in terms of the fractional-order parameters. The fractional-order parameter enhances the oscillator performance by providing an extra degree-of-freedom. Also, the resulting circuits provide independent controllability for the phase difference and the oscillation frequency. Numerical simulations using MATLAB® are performed to study the effect of the fractional-order parameters on the circuit response. Moreover, PSpice simulations are performed on different cases using two different fractional-order capacitors. Selected cases are verified experimentally to confirm the theoretical findings. © 2022 Elsevier Inc. All rights reserved.
A survey on memristor active emulation circuits in the fractional-order domain
Chua postulated a new element called a memristor, contributing flux and charge link. The main characteristic of the memristor is a pinched hysteresis double loop with one pinched point. The memristor’s realization in the fractional-order domain increases the hysteresis loop area’s controllability and frequency range. Besides, the fractional-higher-order memristor is realized, achieving more than a pinched point with changes of the pinched point’s location at different values of a. The commercial memristor device is absent until now. For this purpose, scientists concentrated on modeling the memristor achieving its characteristics, and applied it with other circuit elements. This chapter is intended to study the previously proposed memristor emulator in a fractional-order domain dependent on commercial active building blocks. The memristance emulation circuits are classified into four categories: circuits based on operational amplifiers, second-generation current conveyor family circuits, current-feedback operational amplifiers, and complementary metal-oxide semiconductors. The introduced circuits are compared, also the PSPICE, and experimental results confirm the selected circuits. © 2022 Elsevier Inc. All rights reserved.