Do the Bio-impedance Models Exhibit Pinched Hysteresis?

Recently, pinched hysteresis has been found in the electrical modelling of regular plant tissues. Usually, the biological tissues are characterized in the frequency domain using bio-impedance analyzers without investigating the time domain, which would show the pinched hysteresis. In this paper, the current-voltage analysis of some of the widely known electrical bio-impedance models is studied. The investigated models are the single dispersion Cole-impedance model, the double dispersion Cole-impedance model and the fractional-order simplified Hayden model to prove that these models can not exhibit pinched hysteresis. It is proved mathematically in this paper that there are no pinch-off points that would exist in these models. These results are verified with numerical simulations of three different plants: tomato, carrot and banana, concluding that the bioimpedance modelling needs a nonlinear element to model the pinched hysteresis in the current-voltage behaviour of these tissues. © 2020 IEEE.

CNTFET-based Approximate Ternary Adder Design

Multiple-Valued Logic (MVL) offers better data representation allowing higher information processing within the same amount of digits. With a trade-off in accuracy, approximate computation is a method to improve the power, size, and speed of digital circuits. This paper presents the design of CNTFET-based ternary half adder, full adder, 2-trit carry ripple adder, and 4trit carry ripple adder with different accuracies. The proposed designs are implemented using HSPICE tool and simulated for power consumption, delay, and error analysis. The trade-off between the transistor count and the computation accuracy of the propsoed designs is discussed. Simulation results show that the approximate and corrected approximate designs could significantly improve power-delay product and transistor count compared to their accurate designs. For some cases, approximate and corrected approximate designs have up to 19.8 × improvement in the transistors count and up to 295.3 × improvement in PDP compared to their accurate designs. The corrected designs outperform the approximate ones in terms of accuracy while achieving around 1.5 × improvement in AED. © 2023 IEEE.

CNTFET-based ternary address decoder design

With the end of Moore’s law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power- and time-consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre-decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs. © 2022 John Wiley & Sons Ltd.