For the first time, a generalized admittance Smith chart theory is introduced to represent fractional order circuit elements. The principles of fractional order matching circuits are described. We show that for fractional order ? < 1, a single parallel fractional element can match a wider range of load impedances as compared to its series counterpart. Several matching examples demonstrate the versatility of fractional order series and parallel element matching as compared to the conventional approach. © 2012 IEEE.
On the mathematical modeling of Memristors
Since the fourth fundamental element (Memristor) became a reality by HP labs, and due to its huge potential, its mathematical models became a necessity. In this paper, we provide a simple mathematical model of Memristors characterized by linear dopant drift for sinusoidal input voltage, showing a high matching with the nonlinear SPICE simulations. The frequency response of the Memristor’s resistance and its bounding conditions are derived. The fundamentals of the pinched i-v hysteresis, such as the critical resistances, the hysteresis power and the maximum operating current, are derived for the first time. © 2009 IEEE.
State space modeling of Memristor-based Wien oscillator
State space modeling of Memristor based Wien ‘A’ oscillator has been demonstrated for the first time considering nonlinear ion drift in Memristor. Time dependant oscillating resistance of Memristor is reported in both state space solution and SPICE simulation which plausibly provide the basis of realizing parametric oscillation by Memristor based Wien oscillator. In addition to this part Memristor is shown to stabilize the final oscillation amplitude by means of its nonlinear dynamic resistance which hints for eliminating diode in the feedback network of conventional Wien oscillator. © 2011 IEEE.
Design, implementation and analysis of fully digital 1-D controllable multiscroll chaos
This paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation. For the first time, digital design is exploited to provide real-time controllability of (i) number of scrolls, (ii) position in 1-D space, (iii) Euler step size and (iv) system parameter. The effect of variations in these fields on the maximum Lyapunov exponent (MLE) is analyzed. The system is implemented using Verilog HDL and synthesized on an Xilinx Virtex 4 FPGA, exhibiting area utilization less than 3.5% and high performance with experimentally verified throughput up to 3.33 Gbits/s. This fully digital system enables applications in modulation schemes and chaos-based cryptosystems without analog to digital conversion. © 2011 IEEE.
The effect of numerical techniques on differential equation based chaotic generators
In this paper, we study the effect of the numerical solution accuracy on the digital implementation of differential chaos generators. Four systems are built on a Xilinx Virtex 4 FPGA using Euler, mid-point, and Runge-Kutta fourth order techniques. The twelve implementations are compared based on the FPGA used area, maximum throughput, maximum Lyapunov exponent, and autocorrelation confidence region. Based on circuit performance and the chaotic response of the different implementations, it was found that less complicated numerical solution has better chaotic response and higher throughput. © 2011 IEEE.
Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator
This paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity
Fully digital 1-D, 2-D and 3-D multiscroll chaos as hardware pseudo random number generators
This paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation
Secure DS-CDMA spreading codes using fully digital multidimensional multiscroll chaos
This paper introduces a generalized fully digital hardware implementation of 1-D, 2-D and 3-D multiscroll chaos through sawtooth nonlinearities in a 3rd order ODE with the Euler approximation, wherein low-significance bits pass all NIST SP
HP Memristor mathematical model for periodic signals and DC
Since the fourth fundamental element (Memristor) became a reality by HP labs, and due to its huge potential, its mathematical models became a necessity
Hardware realization of chaos based block cipher for image encryption
Unlike stream ciphers, block ciphers are very essential for parallel processing applications