This paper discusses the influence of the fractional order parameter on conventional chaotic systems
Random number generation based on digital differential chaos
In this paper, we study the effect of the numerical solution accuracy on the digital implementation of differential chaos generators
On the short-term predictability of fully digital chaotic oscillators for pseudo-random number generation
This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation
Mathematics behind the fractional-order smith chart
For the first time, a generalized admittance Smith chart theory is introduced to represent fractional order circuit elements
Fibonacci-based hardware post-processing for non-autonomous signum hyperchaotic system
This paper presents a hardware implementation of a robust non-autonomous hyperchaotic-based PRNG driven by a 256-bit LFSR
Time domain oscillating poles: Stability redefined in Memristor based Wien-oscillators
State space modeling of Memristor based Wien ‘A’ oscillator has been demonstrated for the first time considering nonlinear ion drift in Memristor
Effect of boundary on controlled memristor-based oscillator
Recently, the applications of memristors have spread into many fields and especially in the circuit theory
Memristor-based relaxation oscillators using digital gates
This paper presents two memristor-based relaxation oscillators
Fractional-order RC and RL circuits
This paper is a step forward to generalize the fundamentals of the conventional RC and RL circuits in fractional-order sense. The effect of fractional orders is the key factor for extra freedom, more flexibility, and novelty. The conditions for RC and RL circuits to act as pure imaginary impedances are derived, which are unrealizable in the conventional case. In addition, the sensitivity analyses of the magnitude and phase response with respect to all parameters showing the locations of these critical values are discussed. A qualitative revision for the fractional RC and RL circuits in the frequency domain is provided. Numerical and PSpice simulations are included to validate this study. © Springer Science+Business Media, LLC 2012.
Hardware stream cipher with controllable chaos generator for colour image encryption
This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.