This paper introduces a new encryption/decryption scheme based on a dynamic substitution box concept. Values of the proposed S-Box are different for each sample depending on the behavior of a memristor-based chaotic system. MATLAB simulations and FPGA implementation for the circuit are presented with throughput 4.266 Gbit/s. Also, FPGA realization for encryption/decryption scheme is proposed. Entropy, MSE, correlation coefficient tests are applied on two different input files to examine the efficiency of this cryptosystem. © 2018 IEEE.
Hardware Speech Encryption Using a Chaotic Generator, Dynamic Shift and Bit Permutation
This paper proposes a speech encryption and decryption system, its hardware architecture design and FPGA implementation. The system utilizes Nosé Hoover chaotic generator and/or dynamic shift and bit permutation. The effect of different blocks in the proposed encryption scheme is studied and the security of the system is validated through perceptual and statistical tests. The complete encryption scheme is simulated using Xilinx ISE 14.5 and realized on FPGA Xilinx Kintex 7, presenting the experimental results on the oscilloscope. The efficiency is also validated through hardware resources utilization compared to previous works based on maximum frequency and throughput. © 2018 IEEE.
FPGA realization of ALU for mobile GPU
Arithmetic Logic Unit (ALU) is the most important component of processors
FPGA Implementation of X- and Heart-shapes Controllable Multi-Scroll Attractors
This paper proposes new multi-scrolls chaotic systems which is called the X-shape
Permutation-Only FPGA Realization of Real-Time Speech Encryption
This paper proposes a speech encryption and decryption system, its hardware architecture design and FPGA implementation
FPGA realization of speech encryption based on modified chaotic logistic map
This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations
A Digital Hardware Implementation for A new Mixed-Order Nonlinear 3-D Chaotic System
This paper introduces a new encryption/decryption scheme based on a dynamic substitution box concept
FPGA realization of Caputo and Grünwald-Letnikov operators
2017Abdelaty A.M.Azar A.T.Confrence PaperElwakil A.S.Madian A.H.Ounnas A.Radwan A.G.Said L.A.Tolba M.F.
This paper proposes a hardware platform implementation on FPGA for two fractional-order derivative operators
Security and Efficiency of Feistel Networks Versus Discrete Chaos for Lightweight Speech Encryption
This paper compares examples of non-chaotic and chaotic ciphers from the viewpoint of their suitability for speech encryption, especially in real-time and lightweight cipher systems
Speech Encryption on FPGA Using a Chaotic Generator and S-Box Table
2019Abdel-Gawad A.H.Confrence PaperMadian A.H.Mohamed A.T.Radwan A.G.Saleh H.I.Tolba M.F.Yassin H.M.
In this paper, we proposed a new technique for designing a dynamic S-box depended on the idea of DNA module and Chaotic system to increase its security