K Nearest Neighbors (KNN) algorithm is a straight-forward yet powerful Machine Learning (ML) tool widely used in classification, clustering, and regression applications. In this work, KNN is applied, with three distance metrics, to classify different datasets, experimentally testing each distance metric effect on the classification performance. A static K is applied for the whole dataset optimally chosen based on a 5-fold cross-validation. A reconfigurable hardware realization on field programmable gate array (FPGA) of each distance metric applying selection sort algorithm is proposed. The FPGA realization reaches a throughput up to 4.44 Gbit/sec while only occupying 1% of the Genesys 2 Kintex-7 board area. The algorithm managed to classify all the tested datasets with above 90% accuracy. © 2022 IEEE.
Artificial Neural Network Chaotic PRNG and simple encryption on FPGA
Artificial Neural Networks (ANNs) are remarkably able to fit complex functions, making them useful in various applications and systems. This paper uses ANN to fit the Pehlivan–Uyaroglu Chaotic System (PUCS) to produce an Artificial Neural Network Chaotic Pseudo-Random Number Generator (ANNC-PRNG). The proposed PRNG imitates the PUCS chaotic system’s properties and attractor shape. The proposed ANNC-PRNG is implemented in a simple image encryption system on the Xilinx Kintex-7 Genesys 2 Field Programmable Gate Array (FPGA) board. Hardware realization of an ANN trained on chaotic time series has not been presented before. The proposed ANN can be used for different numerical methods or chaotic systems, including fractional-order systems while keeping the same resources despite the methodsÂ’ complexity or chaotic systemsÂ’ complexity. Extensive testing for the ANNC-PRNG was done to prove the randomness of the produced outputs. The proposed ANNC-PRNG and the encryption system passed various well-established security and statistical tests and produced good results compared to recent similar research. The encryption system is robust against different attacks. The proposed hardware architecture is fast as it reaches a maximum frequency of 12.553 MHz throughput of 301 Mbit/s. © 2023 Elsevier Ltd
Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA
Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts © 2023 Elsevier GmbH