In this paper, an automated universal verification methodology (UVM) tool for rapid functional verification is presented. Now, UVM dominates the verification process but, it is very hard and too complicated to learn. This paper introduces a lightweight UVM tool which allows the user to rapidly verify complex RTL designs and different IPs. Also, it allows the user to perform the simulation for any design under test (DUT). The proposed tool generates the suitable UVM architecture to the DUT with the needed codes. Moreover, it provides the user with statistics about the number of the used classes and methods. Different UVM architectures with different UVM environments are proposed such as the single layer, multilayers, multi-masters multi-slaves and generic UVM architecture. Finally, the tool is tested with automotive IPs and the results show that the tool is very robust and reliable. © 2018 IEEE.
Hamed E.M., Salah K., Madian A.H., Radwan A.G.
generic architecture of UVM; layering protocols; multi masters; multi-slaves; UVM; verification
Proceedings of the International Conference on Microelectronics, ICM, Vol. 2018-December, Art. No. 8704037, PP. 136 to 139, Doi: 10.1109/ICM.2018.8704037