Abstract
This paper presents a hardware implementation of a robust non-autonomous hyperchaotic-based PRNG driven by a 256-bit LFSR. The original chaotic output is post-processed using a novel technique based on the Fibonacci series, bitwise XOR, rotation, and feedback. The proposed post-processing technique preserves the throughput of the system and enhances the randomness in the output which is verified by successfully passing all NIST SP. 800-22 tests. The system is realized on a Xilinx Virtex 4 FPGA achieving throughput up to 13.165 Gbits/s for 16-bit bus-width surpassing previously reported CB-PRNGs. © 2013 IEEE.
Authors
Mansingka A.S., Barakat M.L., Zidan M.A., Radwan A.G., Salama K.N.
Document Type
Confrence Paper
Source
2013 International Conference on IT Convergence and Security, ICITCS 2013, Art. No. 6717834, Doi: 10.1109/ICITCS.2013.6717834