FPGA implementation of fractional-order Chua’s chaotic system


This paper introduces FPGA implementation of fractional order double scrolls chaotic system based on Chua circuit. Grunwald-Letnikov’s (GL) definition is used to generalize the chaotic system equations into the fractional-order domain. Xilinx ISE 14.5 is used to simulate the proposed design and Artix-7 XC7A100T FPGA is used for system realization. Experimental results are presented on digital oscilloscope and the error between theoretical and experimental results is calculated. Also, various interesting attractors are obtained with respect to different parameters values and window sizes. Some techniques have been employed to increase the throughput to 7.685 Gbit/Sec with 96-bits overall output. © 2018 IEEE.


El-Maksoud A.J.A., El-Kader A.A.A., Hassan B.G., Abdelhamed M.A., Rihan N.G., Tolba M.F., Said L.A., Radwan A.G., Abu-Elyazeed M.F.


Chaos; Chua’s circuit; FPGA; Fractional calculus

Document Type

Confrence Paper


2018 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, PP. 1 to 4, Doi: 10.1109/MOCAST.2018.8376632

Scopus Link

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