Abstract
This paper proposes a hardware platform implementation on FPGA for two fractional-order derivative operators. The Grünwald-Letnikov and Caputo definitions are realized for different fractional orders. The realization is based on non-uniform segmentation algorithm with a variable lookup table. A generic implementation for Grünwald-Letnikov is proposed and a 32 bit Fixed Point Booth multiplier radix-4 is used for Caputo implementation. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance and other techniques for area and delay minimization have been employed. A comparison between the two presented architectures is introduced. The proposed designs have been simulated using Xilinx ISE and realized on FPGA Xilinx virtex-5 XC5VLX50T. The total area of 2515 look up tables is achieved for Caputo implementation, and maximum frequency of 54.11 MHz and 1498 slices are achieved for Grünwald-Letnikov architecture. © 2017 IEEE.
Authors
Tolba M.F., Abdelaty A.M., Said L.A., Elwakil A.S., Azar A.T., Madian A.H., Ounnas A., Radwan A.G.
Document Type
Confrence Paper
Source
2017 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017, Art. No. 7937659, Doi: 10.1109/MOCAST.2017.7937659