Exploring the implementation of fractional calculus is essential to be adequately used in several applications. This paper introduces an FPGA design methodology of fractional order multi-scrolls chaotic system. Hardware resources comparison proves the efficiency of the proposed method. The designs are simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx Artix 7. Different interesting attractors are realized under various parametric changes with distinct step sizes for different fractional-orders. To verify the proposed fractional order multi-scrolls chaotic system on FPGA, experimental oscilloscope results have been added. The experimental results show good performance compared with MATLAB simulations and previous works. © 2019 IEEE.
Roshdy M., Tolba M.F., Said L.A., Madian A.H., Radwan A.G.
Chaotic; FPGA; Fractional order; Multi-Scrolls
17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, Art. No. 8961267, Doi: 10.1109/NEWCAS44328.2019.8961267