Memristor-based redundant binary adder


This paper introduces a memristor based ternary adder, which is an essential building block for any arithmetic ternary operations. The proposed ternary adder circuit tries to achieve the theoretical advantages of the ternary system, increase the density and decrease the processing time by using the memristor properties such as its hysteresis and nanotechnology. The general block diagram of the proposed circuit is illustrated based on memristors and its operation has been validated via different examples using PSPICE where simulation results show a great match. © 2013 IEEE.


El-Slehdar A.A., Fouad A.H., Radwan A.G.


Adder circuit; Block diagrams; Building blockes; Memristor; Processing time; Adders; Memristors; Microelectronics; SPICE; Passive filters

Document Type

Confrence Paper


2013 25th International Conference on Microelectronics, ICM 2013, Art. No. 6735002, Doi: 10.1109/ICM.2013.6735002

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