Enhanced hardware implementation of a mixed-order nonlinear chaotic system and speech encryption application


This paper introduces a study for the effect of using different floating-point representations on the chaotic system’s behaviour. Also, it offers a comparison between the attractors at three different orders, (integer, fractional, and mixed-order). This comparison shows the minimum number of bits needed for all parameters to simulate the chaotic attractor in each case. Numerical simulations using Matlab are presented for all discussed chaotic systems. This study opens the door to implement chaotic systems and different applications digitally with low hardware area. The FPGA hardware realization for all integer, fractional, and mixed-order new Wang chaotic system is proposed. The proposed realization achieves about a 10x reduction in the hardware resources of chaotic systems implementation compared with the previous work. Also, the chaotic system at three different orders (integer, fractional, and mixed) are employed in a sound encryption scheme. Two speech files are used to test the scheme which shows good results. They are simulated by Xilinx ISE 14.7 and implemented on Xilinx Vertix-5 FPGA kit using Verilog hardware description language. The three systems show great results in terms of MSE, entropy, correlation coefficient, and pass the NIST test. © 2020 Elsevier GmbH


Elsafty A.H., Tolba M.F., Said L.A., Madian A.H., Radwan A.G.


Chaotic systems; FPGA; Fractional-order applications; Mixed-order; Sound encryption

Document Type



AEU – International Journal of Electronics and Communications, Vol. 125, Art. No. 153347, Doi: 10.1016/j.aeue.2020.153347

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