FPGA Implementation of the Fractional Order Integrator/Differentiator: Two Approaches and Applications


Exploring the use of fractional calculus is essential for it to be used properly in various applications. Implementing the fractional operator D? in FPGA is an important research topic in fractional calculus; in the literature, only a few FPGA implementations have been proposed due to the memory dependence of the fractional order systems. In this paper, FPGA implementations of fractional order integrator/differentiator based on the Grünwald-Letnikov (GL) operator are proposed. Two algorithms are developed based on look-up table and quadratic and piece-wise linear approximation approaches to realize the GL operator and achieve high accuracy, better performance, and efficient usage of FPGA resources and to reduce the memory dependence of fractional order systems. The proposed work shows a maximum absolute error reduction of 91% compared with previous approaches. The proposed building blocks are used to implement a fractional order transfer functions for applications, including a Heavisides inductor-terminated lossy line system, a damped oscillator, a fractional order controller, and a fractional order V-shape multi-scroll chaotic system. © 2018 IEEE.


Tolba M.F., Said L.A., Madian A.H., Radwan A.G.


FPGA; fractional order; GL; PWL

Document Type



IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, Art. No. 8579529, PP. 1484 to 1495, Doi: 10.1109/TCSI.2018.2885013

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