A Universal Fractional-Order Memelement Emulation Circuit

This paper proposes a current-/voltage-controlled universal emulator that can realize any fractional-order memelements (FOME). The proposed emulator consists of second-generation current conveyors (CCII) block, two switches, and a multiplier/divider block. The first switch controls the emulator mode (voltage or current), while, the other controls the type of the emulated FOME. The influence of the fractional-order capacitor (FOC) on the pinched hysteresis loop (PHL) area, is discussed which increases the controllability on the double loop area and the working frequency range. Numerical and PSPICE simulations are presented for selected cases to prove the theoretical findings. © 2019 IEEE.

On Series Connections of Fractional-Order Elements and Memristive Elements

This paper proposes a current-controlled fractional-order memristor emulator based on one active building block. The emulator consists of a multiplication mode current conveyor (MMCC) block with three passive elements. Additionally, the series connection of fractional-order inductor (FOI) and fractional-order capacitor (FOC) with memristive elements in the i-v plane is demonstrated numerically for different cases. Changing the order of the FOC or FOI and its effect on the pinched hysteresis loop area are investigated, which improve the controllability of the double loop area, the location of the pinched point, and the operating frequency range. Numerical, PSPICE simulation results, and experimental verification are investigated for different cases to approve the theoretical findings. Moreover, a sensitivity analysis using Monte Carlo simulations for the tolerance of the discrete components of the memristor emulator is investigated. © 2020 IEEE.

Memristor-CNTFET based Ternary Comparator unit

This paper proposes a new design for ternary logic comparator unit based on memristive threshold logic concept. To provide high-performance design, integrating memristor and Carbon Nano-Tube Field-Effect Transistor, CNTFET, is used. A comparison with other related work is presented to discuss performance aspects. It shows that performance has been improved by 75% compared with the other related work. Therefore, the proposed design is very promising to build high-performance full ternary ALU memristor-based unit. © 2018 IEEE.

FPGA Speech Encryption Realization Based on Variable S-Box and Memristor Chaotic Circuit

This paper introduces a new encryption/decryption scheme based on a dynamic substitution box concept. Values of the proposed S-Box are different for each sample depending on the behavior of a memristor-based chaotic system. MATLAB simulations and FPGA implementation for the circuit are presented with throughput 4.266 Gbit/s. Also, FPGA realization for encryption/decryption scheme is proposed. Entropy, MSE, correlation coefficient tests are applied on two different input files to examine the efficiency of this cryptosystem. © 2018 IEEE.

A Simple BJT Inverse Memristor Emulator and Its Application in Chaotic Oscillators

A generalized inverse memristor emulator is proposed based on two BJT transistors as a diode connected with a first order parallel RC filter. The mathematical model of the circuit is presented where the pinched hysteresis loops (PHLs) with different periodic stimuli are analyzed. The numerical, P-Spice simulations and experimental results are presented indicating that the introduced emulator is a simple voltage-controlled generalized inverse memristor. The results show that the PHLs area is increased with increasing the applied frequency. In addition, the proposed emulator is employed in a simple chaotic circuit. The effect of the inductor’s values on the chaotic system is investigated and the P-Spice simulations are performed to approve the numerical results. © 2019 IEEE.

The modified single input Op-Amps memristor based oscillator

This paper introduces the modified single input Op-Amps memristor based oscillator. The oscillator is realized with ideal, LM741 and current feedback (AD844) Op-Amps where memristors replace resistors. The effect of memristor on the oscillation frequency and the oscillation condition that are totally independent is studied. This helped in studying the whole operation regime of the memristor. The effect of initial conditions on the circuit behavior is discussed. The dynamic poles of the oscillator after resistors replacement are illustrated. Sustained oscillation is obtained and simulated results are nearly matched to the calculated results. © 2013 IEEE.

Memristor-based balanced ternary adder

This paper introduces a memristor based ternary adder, which is an essential building block for any arithmetic ternary operations. The proposed ternary adder circuit tries to achieve the theoretical advantages of the ternary system, increase the density and decrease the processing time by using the memristor properties such as its hysteresis and nanotechnology. The general block diagram of the proposed circuit is illustrated based on memristors and its operation has been validated via different examples using PSPICE where simulation results show a great match. © 2013 IEEE.

On the mathematical modeling of Memristors

Since the fourth fundamental element (Memristor) became a reality by HP labs, and due to its huge potential, its mathematical models became a necessity. In this paper, we provide a simple mathematical model of Memristors characterized by linear dopant drift for sinusoidal input voltage, showing a high matching with the nonlinear SPICE simulations. The frequency response of the Memristor’s resistance and its bounding conditions are derived. The fundamentals of the pinched i-v hysteresis, such as the critical resistances, the hysteresis power and the maximum operating current, are derived for the first time. © 2009 IEEE.

State space modeling of Memristor-based Wien oscillator

State space modeling of Memristor based Wien ‘A’ oscillator has been demonstrated for the first time considering nonlinear ion drift in Memristor. Time dependant oscillating resistance of Memristor is reported in both state space solution and SPICE simulation which plausibly provide the basis of realizing parametric oscillation by Memristor based Wien oscillator. In addition to this part Memristor is shown to stabilize the final oscillation amplitude by means of its nonlinear dynamic resistance which hints for eliminating diode in the feedback network of conventional Wien oscillator. © 2011 IEEE.

CNTFET-based Approximate Ternary Adder Design

Multiple-Valued Logic (MVL) offers better data representation allowing higher information processing within the same amount of digits. With a trade-off in accuracy, approximate computation is a method to improve the power, size, and speed of digital circuits. This paper presents the design of CNTFET-based ternary half adder, full adder, 2-trit carry ripple adder, and 4trit carry ripple adder with different accuracies. The proposed designs are implemented using HSPICE tool and simulated for power consumption, delay, and error analysis. The trade-off between the transistor count and the computation accuracy of the propsoed designs is discussed. Simulation results show that the approximate and corrected approximate designs could significantly improve power-delay product and transistor count compared to their accurate designs. For some cases, approximate and corrected approximate designs have up to 19.8 × improvement in the transistors count and up to 295.3 × improvement in PDP compared to their accurate designs. The corrected designs outperform the approximate ones in terms of accuracy while achieving around 1.5 × improvement in AED. © 2023 IEEE.