FPGA Implementation of Delayed Fractional-Order Financial Chaotic System


This paper proposes digital design and realization on Field-Programmable Gate Array (FPGA) of the Fractional-order (FO) delayed financial chaotic system. The system is solved numerically using the approximated Grünwald-Letnikov (GL) method. For the purpose of FPGA realization, the short memory principle and an approximate GL with limited window size are utilized. Lookup Tables (LUTs) are employed to store the required state values in order to compute the delayed terms. The proposed digital design is implemented on Artix-7 FPGA platform XC7A100T and realized experimentally on the oscilloscope. The proposed FPGA realization demonstrates good hardware resources utilization and a throughput of 1.444672 Gbit/sec. It is efficient in comparison with the recently proposed realization of the FO order Liu et al. system with time delay. © 2020 IEEE.


Roshdy M., Sayed W.S., Said L.A., Madian A.H., Radwan A.G., Dessouky M.


Chaotic; Delayed; FPGA; Fractional calculus

Document Type

Confrence Paper


16th International Computer Engineering Conference, ICENCO 2020, Art. No. 9357375, PP. 51 to 54, Doi: 10.1109/ICENCO49778.2020.9357375

Scopus Link

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