Unlike stream ciphers, block ciphers are very essential for parallel processing applications. In this paper, the first hardware realization of chaotic-based block cipher is proposed for image encryption applications. The proposed system is tested for known cryptanalysis attacks and for different block sizes. When implemented on Virtex-IV, system performance showed high throughput and utilized small area. Passing successfully in all tests, our system proved to be secure with all block sizes. © 2011 IEEE.
Barakat M.L., Radwan A.G., Salama K.N.
Block ciphers; Block sizes; Hardware realization; High throughput; Image encryptions; Parallel processing; Small area; Stream Ciphers; Hardware; Image processing; Microelectronics; Security of data; Cryptography
Proceedings of the International Conference on Microelectronics, ICM, Art. No. 6177386, Doi: 10.1109/ICM.2011.6177386