Abstract
Recently multilevel systems are one of the hottest topics in the digital electronics field. Multi-level logic (MVL) overcomes the issues of interconnections. The ternary system is a promising system where the implementation complexity is low and more information can be stored compared to the binary logic system. In this paper, 4-bit adder has been implemented with CNTFETs and memristors using three different methods; carry-ripple adder, carry-skip adder and carry-lookahead adder. A comparative study between the three adders is introduced in terms of the average power and delay. The adders have been validated with SPICE simulations using VTEAM memristor and Stanford CNTFET transistor models. The carry-lookahead adder (CLA) shows 10x better power-delay product compared to carry ripple and carry-skip adders. The power and temperature variations are studied on the designed circuits. © 2020 IEEE.
Authors
Mohammaden A., Fouda M.E., Said L.A., Radwan A.G.
Keywords
Carry lookahead adder; Carry-skip adder; CNTFET; Memristor; Ternary full adder; Ternary logic gates; VTEAM model
Document Type
Confrence Paper
Source
Midwest Symposium on Circuits and Systems, Vol. 2020-August, Art. No. 9184616, PP. 562 to 565, Doi: 10.1109/MWSCAS48704.2020.9184616