Abstract
This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%. © 2013 IEEE.
Authors
Radwan A.G., Mansingka A.S., Zidan M.A., Salama K.N.
Keywords
Chaotic systems; Circuit oscillations; Chaotic oscillators; Chaotic outputs; Digital implementation; Euler approximation; Optimal parameter; Post processing; Pseudo random number generators; Pseudo-random numbers; Random number generation
Document Type
Confrence Paper
Source
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Art. No. 6815432, PP. 373 to 376, Doi: 10.1109/ICECS.2013.6815432