Area and power consumption are the main challenges in Network on Chip (NoC). Indeed, First Input First Output (FIFO) memory is the key element in NoC. Increasing the FIFO depth, produces an increas in the performance of NoC but at the cost of area and power consumption. This paper proposes a new hybrid CMOS-Memristor based FIFO architecture that consumes low power and has a small size compared to the conventional CMOS-based FIFOs. The predicted area is approximately equal to the half of that wasted in conventional FIFOs. The implementation of FIFO controller module is implemented using HDL. Moreover, the functionality test and the simulation results of the proposed architecture are presented. Simulation is done using ISF Xilinix and Cadence tools. © 2018 IEEE.
Elbtity M.E., Radwan A.G.
CMOS integrated circuits; Electric power utilization; Memristors; Network architecture; Controller modules; Functionality tests; Hybrid CMOS; In networks; Key elements; Low Power; Proposed architectures; Small area; Network-on-chip
Proceedings – IEEE International Symposium on Circuits and Systems, Vol. 2018-May, Art. No. 8351645, Doi: 10.1109/ISCAS.2018.8351645