Abstract
Arithmetic Logic Unit (ALU) is the most important component of processors. All arithmetic and logical computations are performed inside the ALU. This paper presents the design and the implementation of the ALU. The design is based on Approximated Precision Shader and Look-Up Table (LUT) multiplier. The lookup table, Wallace tree, and Carry Look-ahead Adder (CLA) are used in combination to speed up the multiplier operation. The proposed ALU is designed using Verilog and verified using Xilinx Virtex-5 XC5VLX30 FPGA. © 2016 IEEE.
Authors
Tolba M.F., Madian A.H., Radwan A.G.
Keywords
ALU; CLA; FPGA; GPU; LUT Multiplier; Multiplier; Verilog; Xilinx
Document Type
Confrence Paper
Source
2016 3rd International Conference on Advances in Computational Tools for Engineering Applications, ACTEA 2016, Art. No. 7560104, PP. 16 to 20, Doi: 10.1109/ACTEA.2016.7560104