This paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation. For the first time, digital design is exploited to provide real-time controllability of (i) number of scrolls, (ii) position in 1-D space, (iii) Euler step size and (iv) system parameter. The effect of variations in these fields on the maximum Lyapunov exponent (MLE) is analyzed. The system is implemented using Verilog HDL and synthesized on an Xilinx Virtex 4 FPGA, exhibiting area utilization less than 3.5% and high performance with experimentally verified throughput up to 3.33 Gbits/s. This fully digital system enables applications in modulation schemes and chaos-based cryptosystems without analog to digital conversion. © 2011 IEEE.
Mansingka A.S., Radwan A.G., Salama K.N.
Area utilization; Chaos generator; Digital designs; Digital implementation; Digital system; Euler approximation; Maximum Lyapunov exponent; Modulation schemes; Non-Linearity; Step size; Verilog HDL; Digital to analog conversion; Lyapunov methods; Microelectronics
Proceedings of the International Conference on Microelectronics, ICM, Art. No. 6177371, Doi: 10.1109/ICM.2011.6177371