This chapter discusses the analysis and design of memristor-based oscillators which is considered one of the nonlinear analog block required for many applications such as chaotic memristor oscillators and artificial neuron network. The realizations of memristor-based oscillators have been discussed via replacing capacitors with memristors to construct relaxation reactance-less oscillators. The advantages of such oscillators are related to low frequency, nanoscale, and simple designs and can be used in neuromorphic systems. Different topologies of memristor-based relaxation oscillators have been discussed and either symmetric or asymmetric types with analytical formulas of oscillation frequency and condition for oscillations are derived. The analyses of these oscillators are introduced with their numerical simulations, and verified using PSPICE circuit simulations showing a great matching. Moreover, many fundamentals are also discussed such as the effect of boundary dynamics, series and parallel connections as well as power analysis in memristor-based circuits. © 2015, Springer International Publishing Switzerland.
Memristor-based multilevel digital systems
This chapter investigates the advantages of memristor-based digital applications using multi-level arithmetic concepts. Recently, there are huge concerns regarding the memristor in digital signal processing (DSP) circuits to enhance the performance and realize very high density, nonvolatile memories in neural networks. This can be achieved by mapping the high/low logic into the memristor high/low resistances. Recently, the potential to divide the memristance levels to build multilevel digital circuits such as the ternary and redundant circuits are discussed. The concepts have been initiated by designing a half ternary adder based on the memristor; then, the concept is generalized for redundant half adder, full adder, and N-bit adder circuits. The advantages of such circuits that the speed is independent on the operand and parallel processing can be handled efficiently. Moreover, a general approach to build digital functions using mixed memristor-transistor circuits are investigated such as multipliers. © 2015, Springer International Publishing Switzerland.
Memcapacitor based applications
This chapter is divided into three sections focusing on some memcapacitor-based applications. The first one discusses the mathematical analyses and design of resistive-less memcapacitor-based relaxation oscillators where different cases have been investigated and validated. Analytical expressions for the oscillation frequency, duty cycle, stored energy, and conditions of oscillation have been achieved with many numerical examples and circuit simulations. The second section discusses the boundary effect on the analysis and output behavior of memcapacitor-based oscillators compared to the previous case. The last section addresses the memcapacitor-bridge synapses with mathematical analysis, weight programming, and circuit simulations. © 2015, Springer International Publishing Switzerland.
Memristor and inverse memristor: Modeling, implementation and experiments
Pinched hysteresis is considered to be a signature of the existence of memristive behavior. However, this is not completely accurate. In this chapter, we are discussing a general equation taking into consideration all possible cases to model all known elements including memristor. Based on this equation, it is found that an opposite behavior to the memristor can exist in a nonlinear inductor or a nonlinear capacitor (both with quadratic nonlinearity) or a derivative-controlled nonlinear resistor/transconductor which we refer to as the inverse memristor. We discuss the behavior of this new element and introduce an emulation circuit to mimic its behavior. Connecting the conventional elements with the memristor and/or with inverse memeristor either in series or parallel affects the pinched hysteresis lobes where the pinch point moves from the origin and lobes’ area shrinks or widens. Different cases of connecting different elements are discussed clearly especially connecting the memristor and the inverse memristor together either in series or in parallel. New observations and conditions on the memristive behavior are introduced and discussed in detail with different illustrative examples based on numerical, and circuit simulations. © Springer International Publishing AG 2017.
Memcapacitor: Modeling, analysis, and emulators
This chapter reviews the memcapacitor, mathematical representations of time-invariant, physical realizations, and mathematical models. Moreover, the nonlinear boundary effect of the memcapacitor under step, sinusoidal, and general periodic excitation responses are discussed with analytical, numerical, and circuit simulations for different examples. The general analyses of series and parallel connections of memcapacitors are introduced with many examples and circuit simulations. Finally a charge-controlled, memristor-less memcapacitor is introduced and validated through different cases. © 2015, Springer International Publishing Switzerland.
Meminductor: Modeling, analysis, and emulators
This chapter introduces the basic definition of meminductor and its mathematical representation of time-invariant system (Ideal, Generic, and Extended) with some examples. The mathematical model of meminductor and its response under different current excitations (step, sinusoidal, and periodic) are discussed with analytical, numerical, and circuit simulations. Different meminductor emulators are introduced with their mathematical modeling and numerical simulation, and verified using PSPICE simulations. © 2015, Springer International Publishing Switzerland.
Memristor mathematical models and emulators
This chapter introduces different generalized mathematical classes of memristors which can be categorized as: continuous symmetrical models (current and voltage controlled emulators), continuous nonsymmetrical model, switched-memristor model, and fractional-order model with some experimental results. Different emulators with experimental results are discussed based on CCII, discrete components, and MOS realizations. Different analytical expressions, numerical analyses, circuit simulations results as well as experimental results are provided for most of the previous models. © 2015, Springer International Publishing Switzerland.
Memristor: Models, types, and applications
This chapter discusses the main properties of the memristor, a comparison between five recent memristor models, mathematical modeling of the HP memristor with analytical expressions for different excitations, mathematical representations of time-invariant memristor (ideal, generic, and extended), different memristor implementation types, and some memristor-based applications in digital and analog circuits. © 2015, Springer International Publishing Switzerland.
CNTFET-Based Ternary Multiply-and-Accumulate Unit
Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels. © 2022 by the authors. Licensee MDPI, Basel, Switzerland.
CNTFET-based ternary address decoder design
With the end of Moore’s law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power- and time-consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre-decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs. © 2022 John Wiley & Sons Ltd.