Secret image sharing (SIS) conveys a secret image to mutually suspicious receivers by sending meaningless shares to the participants, and all shares must be present to recover the secret. This paper proposes and compares three systems for secret sharing, where a visual cryptography system is designed with a fast recovery scheme as the backbone for all systems. Then, an SIS system is introduced for sharing any type of image, where it improves security using the Lorenz chaotic system as the source of randomness and the generalized Arnold transform as a permutation module. The second SIS system further enhances security and robustness by utilizing SHA-256 and RSA cryptosystem. The presented architectures are implemented on a field programmable gate array (FPGA) to enhance computational efficiency and facilitate real-time processing. Detailed experimental results and comparisons between the software and hardware realizations are presented. Security analysis and comparisons with related literature are also introduced with good results, including statistical tests, differential attack measures, robustness tests against noise and crop attacks, key sensitivity tests, and performance analysis. © The Author(s) 2024.
On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA
This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard 256times 256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out. © 2013 IEEE.
An inductorless CMOS realization of Chua’s circuit
In this paper, an inductorless CMOS realization of Chua’s circuit [IEEE Trans. Circ. Syst. – I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua’s circuit and can generate Rossler or double-scroll attractors by changing a single capacitor’s value. Variables are represented in the current domain to facilitate adding or subtracting variables. New Gm-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as ±1.5 V. Transistor-level simulation results using PSpice in 0.5 ?m Mietec process are presented. © 2003 Published by Elsevier Science Ltd.
MOS realization of the conjectured simplest chaotic equation
This paper presents a general block diagram of a third-order linear differential equation using current mode techniques. The realization of the conjectured simplest chaotic equation of Elwakil and Kennedy based on G m – C technology is given. The metal oxide semiconductor circuit is composed of 20 transistors and three grounded capacitors, can operate from a supply voltage as low as ± 1.5 V, and covers a very wide range of frequencies. PSpice simulation results using 0.5 ?m Mietec technology are given. A numerical solution is also included to verify the circuit operation.
MOS realization of the double-scroll-like chaotic equation
This brief presents a new chaotic circuit based on Gm-C integrators. The circuit realizes the double-scroll-like chaotic equation presented in [1], [2]. The mentioned equation describes double-scroll dynamics with a simple mathematical model. The proposed circuit uses a current-mode technique that is suitable for integrated circuit implementation and high-frequency operation using low supply voltage. A general block diagram is presented based on Gm-C integrators. Its realization using MOS transistors and three grounded capacitors is also given. Simulation results to demonstrate the practicality of the circuit are included.
On some generalized discrete logistic maps
Recently, conventional logistic maps have been used in different vital applications like modeling and security. However, unfortunately the conventional logistic maps can tolerate only one changeable parameter. In this paper, three different generalized logistic maps are introduced with arbitrary powers which can be reduced to the conventional logistic map. The added parameter (arbitrary power) increases the degree of freedom of each map and gives us a versatile response that can fit many applications. Therefore, the conventional logistic map is considered only a special case from each proposed map. This new parameter increases the flexibility of the system, and illustrates the performance of the conventional system within any required neighborhood. Many cases will be illustrated showing the effect of the arbitrary power and the equation parameter on the number of equilibrium points, their locations, stability conditions, and bifurcation diagrams up to the chaotic behavior. © 2012.
Hardware stream cipher with controllable chaos generator for colour image encryption
This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.
Reconfigurable chaotic pseudo random number generator based on FPGA
This paper presents an FPGA Pseudo Random Number Generator (PRNG) that is based on the Lorenz and Lü chaotic systems. These two systems are used to generate four different 3D chaotic attractors. One attractor is generated from Lorenz while the other three attractors are generated from Lü. The output attractor of the proposed PRNG can be reconfigured during real time operation using an efficient hardwired shifting and multiplexing scheme. Furthermore, in order to exploit the proposed reconfiguration feature, the proposed PRNG has been embedded in an FPGA cascaded encryption processor that ciphers the input data from one up to four times successively. In each ciphering operation the PRNG is set to a new configuration and is initialized according to a part of the encryption key. The size of the encryption key can be varied according to the number of required ciphering operations. The proposed PRNG has been realized using VHDL, synthesized on Xilinx using the FPGA device XC5VLX50T, and analyzed using MATLAB and the NIST statistical suite. The proposed PRNG has utilized only 1.4% from the FPGA’s slices, achieved an operating frequency up to 78 MHz, and successfully passed all the NIST statistical tests. © 2018 Elsevier GmbH
Modified kinetic-hydraulic UASB reactor model for treatment of wastewater containing biodegradable organic substrates
This paper addresses a modified kinetic-hydraulic model for up-flow anaerobic sludge blanket (UASB) reactor aimed to treat wastewater of biodegradable organic substrates as acetic acid based on Van der Meer model incorporated with biological granules inclusion. This dynamic model illustrates the biomass kinetic reaction rate for both direct and indirect growth of microorganisms coupled with the amount of biogas produced by methanogenic bacteria in bed and blanket zones of reactor. Moreover, the pH value required for substrate degradation at the peak specific growth rate of bacteria is discussed for Andrews’ kinetics. The sensitivity analyses of biomass concentration with respect to fraction of volume of reactor occupied by granules and up-flow velocity are also demonstrated. Furthermore, the modified mass balance equations of reactor are applied during steady state using Newton Raphson technique to obtain a suitable degree of freedom for the modified model matching with the measured results of UASB Sanhour wastewater treatment plant in Fayoum, Egypt. © IWA Publishing 2016.
Hardware realization of a secure and enhanced s-box based speech encryption engine
This paper presents a secure and efficient substitution box (s-box) for speech encryption applications. The proposed s-box data changes every clock cycle to swap the input signal with different data, where it generated based on a new algorithm and a memristor chaotic system. Bifurcation diagrams for all memristor chaotic system parameters are introduced to stand for the chaotic range of each parameter. Moreover, the effect of each component inside the proposed encryption system is studied, and the security of the system is validated through perceptual and statistical tests. The size of the encryption key is 175 bits to meet the global standards for the optimum encryption key width (> 128). MATLAB software is used to calculate entropy, MSE, and correlation coefficient. Both chaotic circuit and encryption/decryption schemes are designed using Verilog HDL and simulated by Xilinx ISE 14.7. Xilinx Virtex 5 FPGA kit is used to realize the proposed algorithm with a throughput 0.536 of Gbit/s. The cryptosystem is tested using two different speech files to examine its efficiency. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.