This paper introduces a new generalized complex logistic map and the FPGA realization of a corresponding fractal generation application. The chaotic properties of the proposed map are studied through the stability conditions, bifurcation behavior and maximum Lyapunov exponent (MLE). A relation between the mathematical analysis and fractal behavior is demonstrated, which enables formulating the fractal limits. A compact fractal generation process is presented, which results in designing and implementing an optimized hardware architecture. An efficient FPGA implementation of the fractal behavior is validated experimentally on Artix-7 FPGA board. Two examples of fractal implementation are verified, yielding frequencies of 34.593 MHz and 31.979 MHz and throughputs of 0.415 Gbit/s, 0.384 Gbit/s. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications. © 2021 Elsevier Ltd
FPGA REALIZATION OF COMPLEX LOGISTIC MAP FRACTAL BEHAVIOR
This paper studies the capability of digital architecture to mimic fractal behavior. As chaotic attractors realized digitally had opened many tracks, digital designs mimicking fractals may ultimately achieve the same. This study is based on a complex single-dimensional discrete chaotic system known as the generalized positive logistic map. The fractals realized from this system are linked to the results of the mathematical analysis to understand the fractal behavior with different variations. A digital hardware architecture manifesting the fractal behavior is achieved on FPGA, showing a fractal entity experimentally. With this digital realization, it is hoped that fractals can follow the example of chaotic attractors digital applications. © 2022 World Scientific Publishing Company.
Numerical Sensitivity Analysis and Hardware Verification of a Transiently-Chaotic Attractor
We introduce a new chaotic system with nonhyperbolic equilibrium and study its sensitivity to different numerical integration techniques prior to implementing it on an FPGA. We show that the discretization method used in numerically integrating the set of differential equations in MATLAB and Mathematica does not yield chaotic behavior except when a low accuracy Euler method is used. More accurate higher-order numerical algorithms (such as midpoint and fourth-order Runge-Kutta) result in divergence in both MATLAB and Mathematica (but not Python), which agrees with the divergence observed in an analog circuit implementation of the system. However, a fixed-point digital FPGA implementation confirms the chaotic behavior of the system using Euler and fourth-order Runge-Kutta realizations. Therefore, the increased sensitivity of chaotic systems with nonhyperbolic equilibrium should be carefully considered for reproducibility. © 2022 World Scientific Publishing Company.
Generalized two-port network based fractional order filters
This paper proposes a general prototype fractional order filter based on a two-port network concept with four external impedances. Three induced classifications from the general prototype are extracted with one, two and three external impedances, achieving ten possible generalized topologies. The external impedances are fractional-order elements and resistors. There are forty-six filters divided into twenty-two and twenty-four different general fractional filters of order “?” and order “? + ?”, respectively. The general transfer functions, the necessary network conditions, and the critical frequencies are presented for each topology in terms of the transmission matrix parameters of a general two-port network and the fractional order parameters. These aspects add extra degrees of freedom, which increase the design flexibility and controllability; it is up to the designer to select any network suitable for his application. Six special cases of two-port networks based on the second generation current conveyor (CCII) active building block are synthesized to realize the proposed topologies. CCII family has four members that yield twenty-four different transmission matrices, resulting 480 filters. Due to the large number of the introduced filters, selected cases are investigated in detail to validate the theoretical findings through numerical simulations, Spice simulations, and experimental results. © 2019 Elsevier GmbH
Correction to: Stability analysis of fractional-order Colpitts oscillators (Analog Integrated Circuits and Signal Processing, (2019), 101, 2, (267-279), 10.1007/s10470-019-01501-2)
Unfortunately, in the original version of the article some typos occurred. The typos have been corrected with this erratum. Below are the corrections:(Formula presented.). © 2019, Springer Science+Business Media, LLC, part of Springer Nature.
Fractional order oscillators based on operational transresistance amplifiers
In this paper, a general analysis of the fractional order operational transresistance amplifiers (OTRA) based oscillator is presented and validated through eight different circuits which represent two classifications according to the number of OTRAs. The general analytical formulas of the oscillation frequency, condition as well as the phase difference are illustrated for each case and summarized in tables. One of the advantages of the fractional-order circuit is the extra degrees of freedom added from the fractional-order parameters. Moreover different special cases {? = ? ? 1, ? ? ? = 1, ? ? ? = 1} are investigated where the conventional case ? = ? = 1 is included in all of them. Also, the effect of the fractional order parameter on the phase difference between the two oscillator outputs is presented which increases the design flexibility and controllability. The effect of the non-ideal characteristics associated with OTRA on the presented oscillator is also studied. A comparison between the fractional order oscillators with their integer order counterpart is also presented to verify the advantages of the added fractional order parameters. Numerical and spice simulations are given to validate the presented analysis. © 2015 Elsevier GmbH.
Fractional Order Oscillator Design Based on Two-Port Network
In this paper, a general analysis of the generation for all possible fractional order oscillators based on two-port network is presented. Three different two-port network classifications are used with three external single impedances, where two are fractional order capacitors and a resistor. Three possible impedance combinations for each classification are investigated, which give nine possible oscillators. The characteristic equation, oscillation frequency and condition for each presented topology are derived in terms of the transmission matrix elements and the fractional order parameters ? and ?. Mapping between some cases is also illustrated based on similarity in the characteristic equation. The use of fractional order elements ? and ? adds extra degrees of freedom, which increases the design flexibility and frequency band, and provides extra constraints on the phase difference. Study of four different active elements, such as voltage-controlled current source, gyrator, op-amp-based network, and second-generation current-conveyor-based network, serve as a two-port network is presented. The general analytical formulas of the oscillation frequency and condition as well as the phase difference between the two oscillatory outputs are derived and summarized in tables for each designed oscillator network. A comparison between fractional order oscillators with their integer order counterparts is also illustrated where some designs cannot work in the integer case. Numerical Spice simulations and experimental results are given to validate the presented analysis. © 2015, Springer Science+Business Media New York.
Three Fractional-Order-Capacitors-Based Oscillators with Controllable Phase and Frequency
This paper presents a generalization of six well-known quadrature third-order oscillators into the fractional-order domain. The generalization process involves replacement of three integer-order capacitors with fractional-order ones. The employment of fractional-order capacitors allows a complete tunability of oscillator frequency and phase. The presented oscillators are implemented with three active building blocks which are op-Amp, current feedback operational amplifier (CFOA) and second generation current conveyor (CCII). The general state matrix, oscillation frequency and condition are deduced in terms of the fractional-order parameters. The extra degree of freedom provided by the fractional-order elements increases the design flexibility. Eight special cases including the integer case are illustrated with their numerical discussions. Three different phases are produced with fixed sum of 2p which can be completely controlled by fractional-order elements. A general design procedure is introduced to design an oscillator with a specific phase and frequency. Two general design cases are discussed based on exploiting the degrees of freedom introduced by the fractional order to obtain the required design. Spice circuit simulations with experimental results for some special cases are presented to validate the theoretical findings. © 2017 World Scientific Publishing Company.
A Study on Fractional Power-Law Applications and Approximations
The frequency response of the fractional-order power-law filter can be approximated by different techniques, which eventually affect the expected performance. Fractional-order control systems introduce many benefits for applications like compensators to achieve robust frequency and additional degrees of freedom in the tuning process. This paper is a comparative study of five of these approximation techniques. The comparison focuses on their magnitude error, phase error, and implementation complexity. The techniques under study are the Carlson, continued fraction expansion (CFE), Padé, Charef, and MATLAB curve-fitting tool approximations. Based on this comparison, the recommended approximation techniques are the curve-fitting MATLAB tool and the continued fraction expansion (CFE). As an application, a low-pass power-law filter is realized on a field-programmable analog array (FPAA) using two techniques, namely the curve-fitting tool and the CFE. The experiment aligns with and validates the numerical results. © 2024 by the authors.
DISH: Digital image steganography using stochastic-computing with high-capacity
Stochastic computing is a relatively new approach to computing that has gained interest in recent years due to its potential for low-power and high-noise environments. It is a method of computing that uses probability to represent and manipulate data, therefore it has applications in areas such as signal processing, machine learning, and cryptography. Stochastic steganography involves hiding a message within a cover image using a statistical model. Unlike traditional steganography techniques that use deterministic algorithms to embed the message, stochastic steganography uses a probabilistic approach to hide the message in a way that makes it difficult for an adversary to detect. Due to this error robustness and large bit streams stochastic computing, they are well suited for high capacity and secure image steganography. In this paper, as per the authors’ best knowledge, image steganography using stochastic computing based on linear feedback shift register (LFSR) is proposed for the first time. In the proposed technique, the cover image is converted to stochastic representation instead of the binary one, and then a secret image is embedded in it. The resulting stego image has a high PSNR value transmitted with no visual trace of the hidden image. The final results are stego image with PSNR starting from 30 dB and a maximum payload up to 40 bits per pixel (bpp) with an effective payload up to 28 bpp. The proposed method achieves high security and high capability of the number of stored bits in each pixel. Thus, the proposed method can prove a vital solution for high capacity and secure image steganography, which can then be extended to other types of steganography. © 2024, The Author(s).