This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.
Reconfigurable chaotic pseudo random number generator based on FPGA
This paper presents an FPGA Pseudo Random Number Generator (PRNG) that is based on the Lorenz and Lü chaotic systems. These two systems are used to generate four different 3D chaotic attractors. One attractor is generated from Lorenz while the other three attractors are generated from Lü. The output attractor of the proposed PRNG can be reconfigured during real time operation using an efficient hardwired shifting and multiplexing scheme. Furthermore, in order to exploit the proposed reconfiguration feature, the proposed PRNG has been embedded in an FPGA cascaded encryption processor that ciphers the input data from one up to four times successively. In each ciphering operation the PRNG is set to a new configuration and is initialized according to a part of the encryption key. The size of the encryption key can be varied according to the number of required ciphering operations. The proposed PRNG has been realized using VHDL, synthesized on Xilinx using the FPGA device XC5VLX50T, and analyzed using MATLAB and the NIST statistical suite. The proposed PRNG has utilized only 1.4% from the FPGA’s slices, achieved an operating frequency up to 78 MHz, and successfully passed all the NIST statistical tests. © 2018 Elsevier GmbH
DISH: Digital image steganography using stochastic-computing with high-capacity
Stochastic computing is a relatively new approach to computing that has gained interest in recent years due to its potential for low-power and high-noise environments. It is a method of computing that uses probability to represent and manipulate data, therefore it has applications in areas such as signal processing, machine learning, and cryptography. Stochastic steganography involves hiding a message within a cover image using a statistical model. Unlike traditional steganography techniques that use deterministic algorithms to embed the message, stochastic steganography uses a probabilistic approach to hide the message in a way that makes it difficult for an adversary to detect. Due to this error robustness and large bit streams stochastic computing, they are well suited for high capacity and secure image steganography. In this paper, as per the authors’ best knowledge, image steganography using stochastic computing based on linear feedback shift register (LFSR) is proposed for the first time. In the proposed technique, the cover image is converted to stochastic representation instead of the binary one, and then a secret image is embedded in it. The resulting stego image has a high PSNR value transmitted with no visual trace of the hidden image. The final results are stego image with PSNR starting from 30 dB and a maximum payload up to 40 bits per pixel (bpp) with an effective payload up to 28 bpp. The proposed method achieves high security and high capability of the number of stored bits in each pixel. Thus, the proposed method can prove a vital solution for high capacity and secure image steganography, which can then be extended to other types of steganography. © 2024, The Author(s).
Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA
Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts © 2023 Elsevier GmbH
Software and hardware realizations for different designs of chaos-based secret image sharing systems
Secret image sharing (SIS) conveys a secret image to mutually suspicious receivers by sending meaningless shares to the participants, and all shares must be present to recover the secret. This paper proposes and compares three systems for secret sharing, where a visual cryptography system is designed with a fast recovery scheme as the backbone for all systems. Then, an SIS system is introduced for sharing any type of image, where it improves security using the Lorenz chaotic system as the source of randomness and the generalized Arnold transform as a permutation module. The second SIS system further enhances security and robustness by utilizing SHA-256 and RSA cryptosystem. The presented architectures are implemented on a field programmable gate array (FPGA) to enhance computational efficiency and facilitate real-time processing. Detailed experimental results and comparisons between the software and hardware realizations are presented. Security analysis and comparisons with related literature are also introduced with good results, including statistical tests, differential attack measures, robustness tests against noise and crop attacks, key sensitivity tests, and performance analysis. © The Author(s) 2024.
On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA
This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard 256times 256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out. © 2013 IEEE.
An inductorless CMOS realization of Chua’s circuit
In this paper, an inductorless CMOS realization of Chua’s circuit [IEEE Trans. Circ. Syst. – I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua’s circuit and can generate Rossler or double-scroll attractors by changing a single capacitor’s value. Variables are represented in the current domain to facilitate adding or subtracting variables. New Gm-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as ±1.5 V. Transistor-level simulation results using PSpice in 0.5 ?m Mietec process are presented. © 2003 Published by Elsevier Science Ltd.
Chaotic Dynamics and FPGA Implementation of a Fractional-Order Chaotic System with Time Delay
This article proposes a numerical solution approach and Field Programmable Gate Array implementation of a delayed fractional-order system. The proposed method is amenable to a sufficiently efficient hardware realization. The system’s numerical solution and hardware realization have two requirements. First, the delay terms are implemented by employing LookUp Tables to keep the already required delayed samples in the dynamical equations. Second, the fractional derivative is numerically approximated using Grünwald-Letnikov approximation with a memory window size, L, according to the short memory principle such that it balances between accuracy and efficiency. Bifurcation diagrams and spectral entropy validate the chaotic behaviour of the system for commensurate and incommensurate orders. Additionally, the dynamic behaviour of the system is studied versus the delay parameter, ?, and the window size, L. The system is realized on Nexys 4 Artix-7 FPGA XC7A100T with throughput 1.2 Gbit/s and hardware resources utilization 15% from the total LookUp Tables and 4% from the slice registers. Oscilloscope experimental results verify the numerical solution of the delayed fractional-order system. The amenability to digital hardware realization, which is experimentally validated in this article, is added to the system’s advantages and encourages its utilization in future digital applications such as chaos control and synchronization and chaos-based communication applications. © 2020 IEEE.
Self-Reproducing Hidden Attractors in Fractional-Order Chaotic Systems Using Affine Transformations
This article proposes a unified approach for hidden attractors control in fractional-order chaotic systems. Hidden attractors have small basins of attractions and are very sensitive to initial conditions and parameters. That is, they can be easily drifted from chaotic behavior into another type of dynamics, which is not suitable for encryption applications that require quite wide initial conditions and parameters ranges for encryption key design. Hence, a systematic coordinate affine transformation framework is utilized to construct transformed systems with self-reproducing attractors. Simulation results of two three-dimensional fractional-order chaotic systems with hidden attractors validate that the proposed framework supports attractors geometric structure design and multi-wing generation. Hidden attractor size, polarity, phase, shape and position control while preserving the chaotic dynamics is indicated by strange attractors, spectral entropy, maximum Lyapunov exponent and bifurcation diagrams. Simulations demonstrate the capability of multi-wing generation from fractional-order hidden attractors with no equilibria using non-autonomous parameters as opposed to the classical equilibria extension techniques suitable only for self-excited attractors. The self-reproduced multiple wings can share the same center point or be distributed along an arbitrary line, curve or surface thanks to the non-autonomous translation parameters. Multi-wing attractors widen the basin of attraction and enlarge the state space volume. For practical applications, the proposed technique makes fractional-order systems with hidden attractors suitable for circuit implementations that require specific signal level and polarity conditions. In addition, for digital encryption applications, the relatively wide range of the extra parameters enhances the key space and hence the robustness against brute force attacks. © 2020 IEEE.
Circuit realization and FPGA-based implementation of a fractional-order chaotic system for cancellable face recognition
Biometric security has been developed in recent years with the emergence of cancellable biometric concepts. The idea of the cancellable biometric traits is concerned with creating encrypted or distorted traits of the original ones to protect them from hacking techniques. So, encrypted or distorted biometric traits are stored in databases instead of the original ones. This can be accomplished through non-invertible transforms or encryption schemes. In this paper, a cancellable face recognition algorithm is introduced based on face image encryption through a fractional-order multi-scroll chaotic system. The fundamental concept is to create random keys that will be XORed with the three components of color face images (red, green, and blue) to obtain encrypted face images. These random keys are generated from the Least Significant Bits of all state variables of a proposed fractional-order multi-scroll chaotic system. Lastly, the encrypted color components of face images are combined to produce a single cancellable trait for each color face image. The results of encryption with the proposed system are full-encrypted face images that are suitable for cancellable biometric applications. The strength of the proposed system is that it is extremely sensitive to the user’s selected initial conditions. The numerical simulation of the proposed chaotic system is done with MATLAB. Phase and bifurcation diagrams are used to analyze the dynamic performance of the proposed fractional-order multi-scroll chaotic system. Furthermore, we realized the hardware circuit of the proposed chaotic system on the PSpice simulator. The proposed chaotic system can be implemented on Field Programmable Gate Arrays (FPGAs). To model our generator, we can use Verilog Hardware Description Language HDL, Xilinx ISE 14.7 and Xilinx FPGA Artix-7 XC7A100T based on Grunwald-Letnikov algorithms for mathematical analysis. The numerical simulation, the circuit simulation and the hardware experimental results confirm each other. Cancellable face recognition based on the proposed fractional-order chaotic system has been implemented on FERET, LFW, and ORL datasets, and the results are compared with those of other schemes. Some evaluation metrics containing Equal Error Rate (EER), and Area under the Receiver Operating Characteristic (AROC) curve are used to assess the cancellable biometric system. The numerical results of these metrics show EER levels close to zero and AROC values of 100%. In addition, the encryption scheme is highly efficient. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.