This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard 256times 256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out. © 2013 IEEE.
An inductorless CMOS realization of Chua’s circuit
In this paper, an inductorless CMOS realization of Chua’s circuit [IEEE Trans. Circ. Syst. – I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua’s circuit and can generate Rossler or double-scroll attractors by changing a single capacitor’s value. Variables are represented in the current domain to facilitate adding or subtracting variables. New Gm-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as ±1.5 V. Transistor-level simulation results using PSpice in 0.5 ?m Mietec process are presented. © 2003 Published by Elsevier Science Ltd.
MOS realization of the conjectured simplest chaotic equation
This paper presents a general block diagram of a third-order linear differential equation using current mode techniques. The realization of the conjectured simplest chaotic equation of Elwakil and Kennedy based on G m – C technology is given. The metal oxide semiconductor circuit is composed of 20 transistors and three grounded capacitors, can operate from a supply voltage as low as ± 1.5 V, and covers a very wide range of frequencies. PSpice simulation results using 0.5 ?m Mietec technology are given. A numerical solution is also included to verify the circuit operation.
MOS realization of the double-scroll-like chaotic equation
This brief presents a new chaotic circuit based on Gm-C integrators. The circuit realizes the double-scroll-like chaotic equation presented in [1], [2]. The mentioned equation describes double-scroll dynamics with a simple mathematical model. The proposed circuit uses a current-mode technique that is suitable for integrated circuit implementation and high-frequency operation using low supply voltage. A general block diagram is presented based on Gm-C integrators. Its realization using MOS transistors and three grounded capacitors is also given. Simulation results to demonstrate the practicality of the circuit are included.
On some generalized discrete logistic maps
Recently, conventional logistic maps have been used in different vital applications like modeling and security. However, unfortunately the conventional logistic maps can tolerate only one changeable parameter. In this paper, three different generalized logistic maps are introduced with arbitrary powers which can be reduced to the conventional logistic map. The added parameter (arbitrary power) increases the degree of freedom of each map and gives us a versatile response that can fit many applications. Therefore, the conventional logistic map is considered only a special case from each proposed map. This new parameter increases the flexibility of the system, and illustrates the performance of the conventional system within any required neighborhood. Many cases will be illustrated showing the effect of the arbitrary power and the equation parameter on the number of equilibrium points, their locations, stability conditions, and bifurcation diagrams up to the chaotic behavior. © 2012.
Hardware stream cipher with controllable chaos generator for colour image encryption
This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.
Reconfigurable chaotic pseudo random number generator based on FPGA
This paper presents an FPGA Pseudo Random Number Generator (PRNG) that is based on the Lorenz and Lü chaotic systems. These two systems are used to generate four different 3D chaotic attractors. One attractor is generated from Lorenz while the other three attractors are generated from Lü. The output attractor of the proposed PRNG can be reconfigured during real time operation using an efficient hardwired shifting and multiplexing scheme. Furthermore, in order to exploit the proposed reconfiguration feature, the proposed PRNG has been embedded in an FPGA cascaded encryption processor that ciphers the input data from one up to four times successively. In each ciphering operation the PRNG is set to a new configuration and is initialized according to a part of the encryption key. The size of the encryption key can be varied according to the number of required ciphering operations. The proposed PRNG has been realized using VHDL, synthesized on Xilinx using the FPGA device XC5VLX50T, and analyzed using MATLAB and the NIST statistical suite. The proposed PRNG has utilized only 1.4% from the FPGA’s slices, achieved an operating frequency up to 78 MHz, and successfully passed all the NIST statistical tests. © 2018 Elsevier GmbH
Optimization of Double fractional-order Image Enhancement System
Image enhancement is a vital process that serves as a tool for improving the quality of a lot of real-life applications. Fractional calculus can be utilized in enhancing images using fractional order kernels, adding more controllability to the system, due to the flexible choice of the fractional order parameter, which adds extra degrees of freedom. The proposed system merges two fractional order kernels which helps in image enhancement techniques, and the contribution of this work is based on the study of how to optimize this process. The optimization of the two fractional kernels was done using the neural network optimization algorithm (NNA) to utilize the best order for the two kernels. In this paper, three fractional kernels are studied to highlight the performance of image enhancement using fractional kernels against different metrics. Furthermore, three different combinations of two kernels are combined and studied to enhance the metrics score by utilizing two different fractional orders for each kernel. Various optimization algorithms are used to obtain the optimum fractional order for both single and combined kernels. Using the constrained NNA, the evaluation metrics of the image enhancement show a 33% increase in measure of enhancement metric (EME), 21% increase in contrast, and 4% increase in average gradient compared to the best-achieved metrics by the literature while keeping the similarity metric above 0.75. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.
Chaotic Dynamics and FPGA Implementation of a Fractional-Order Chaotic System with Time Delay
This article proposes a numerical solution approach and Field Programmable Gate Array implementation of a delayed fractional-order system. The proposed method is amenable to a sufficiently efficient hardware realization. The system’s numerical solution and hardware realization have two requirements. First, the delay terms are implemented by employing LookUp Tables to keep the already required delayed samples in the dynamical equations. Second, the fractional derivative is numerically approximated using Grünwald-Letnikov approximation with a memory window size, L, according to the short memory principle such that it balances between accuracy and efficiency. Bifurcation diagrams and spectral entropy validate the chaotic behaviour of the system for commensurate and incommensurate orders. Additionally, the dynamic behaviour of the system is studied versus the delay parameter, ?, and the window size, L. The system is realized on Nexys 4 Artix-7 FPGA XC7A100T with throughput 1.2 Gbit/s and hardware resources utilization 15% from the total LookUp Tables and 4% from the slice registers. Oscilloscope experimental results verify the numerical solution of the delayed fractional-order system. The amenability to digital hardware realization, which is experimentally validated in this article, is added to the system’s advantages and encourages its utilization in future digital applications such as chaos control and synchronization and chaos-based communication applications. © 2020 IEEE.
Self-Reproducing Hidden Attractors in Fractional-Order Chaotic Systems Using Affine Transformations
This article proposes a unified approach for hidden attractors control in fractional-order chaotic systems. Hidden attractors have small basins of attractions and are very sensitive to initial conditions and parameters. That is, they can be easily drifted from chaotic behavior into another type of dynamics, which is not suitable for encryption applications that require quite wide initial conditions and parameters ranges for encryption key design. Hence, a systematic coordinate affine transformation framework is utilized to construct transformed systems with self-reproducing attractors. Simulation results of two three-dimensional fractional-order chaotic systems with hidden attractors validate that the proposed framework supports attractors geometric structure design and multi-wing generation. Hidden attractor size, polarity, phase, shape and position control while preserving the chaotic dynamics is indicated by strange attractors, spectral entropy, maximum Lyapunov exponent and bifurcation diagrams. Simulations demonstrate the capability of multi-wing generation from fractional-order hidden attractors with no equilibria using non-autonomous parameters as opposed to the classical equilibria extension techniques suitable only for self-excited attractors. The self-reproduced multiple wings can share the same center point or be distributed along an arbitrary line, curve or surface thanks to the non-autonomous translation parameters. Multi-wing attractors widen the basin of attraction and enlarge the state space volume. For practical applications, the proposed technique makes fractional-order systems with hidden attractors suitable for circuit implementations that require specific signal level and polarity conditions. In addition, for digital encryption applications, the relatively wide range of the extra parameters enhances the key space and hence the robustness against brute force attacks. © 2020 IEEE.