Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA

2024Ismail S.M.JournalMadian A.H.Radwan A.G.Said L.A.Yacoub M.H.

Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts © 2023 Elsevier GmbH

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

2021JournalMadian A.H.Radwan A.G.Rezk A.A.Soliman A.M.

This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard 256times 256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out. © 2013 IEEE.

Reconfigurable chaotic pseudo random number generator based on FPGA

2019JournalMadian A.H.Radwan A.G.Rezk A.A.Soliman A.M.

This paper presents an FPGA Pseudo Random Number Generator (PRNG) that is based on the Lorenz and Lü chaotic systems. These two systems are used to generate four different 3D chaotic attractors. One attractor is generated from Lorenz while the other three attractors are generated from Lü. The output attractor of the proposed PRNG can be reconfigured during real time operation using an efficient hardwired shifting and multiplexing scheme. Furthermore, in order to exploit the proposed reconfiguration feature, the proposed PRNG has been embedded in an FPGA cascaded encryption processor that ciphers the input data from one up to four times successively. In each ciphering operation the PRNG is set to a new configuration and is initialized according to a part of the encryption key. The size of the encryption key can be varied according to the number of required ciphering operations. The proposed PRNG has been realized using VHDL, synthesized on Xilinx using the FPGA device XC5VLX50T, and analyzed using MATLAB and the NIST statistical suite. The proposed PRNG has utilized only 1.4% from the FPGA’s slices, achieved an operating frequency up to 78 MHz, and successfully passed all the NIST statistical tests. © 2018 Elsevier GmbH

Hardware realization of a secure and enhanced s-box based speech encryption engine

2021Elsafty A.H.JournalMadian A.H.Radwan A.G.Said L.A.Tolba M.F.

This paper presents a secure and efficient substitution box (s-box) for speech encryption applications. The proposed s-box data changes every clock cycle to swap the input signal with different data, where it generated based on a new algorithm and a memristor chaotic system. Bifurcation diagrams for all memristor chaotic system parameters are introduced to stand for the chaotic range of each parameter. Moreover, the effect of each component inside the proposed encryption system is studied, and the security of the system is validated through perceptual and statistical tests. The size of the encryption key is 175 bits to meet the global standards for the optimum encryption key width (> 128). MATLAB software is used to calculate entropy, MSE, and correlation coefficient. Both chaotic circuit and encryption/decryption schemes are designed using Verilog HDL and simulated by Xilinx ISE 14.7. Xilinx Virtex 5 FPGA kit is used to realize the proposed algorithm with a throughput 0.536 of Gbit/s. The cryptosystem is tested using two different speech files to examine its efficiency. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.