Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts © 2023 Elsevier GmbH
Software and hardware realizations for different designs of chaos-based secret image sharing systems
Secret image sharing (SIS) conveys a secret image to mutually suspicious receivers by sending meaningless shares to the participants, and all shares must be present to recover the secret. This paper proposes and compares three systems for secret sharing, where a visual cryptography system is designed with a fast recovery scheme as the backbone for all systems. Then, an SIS system is introduced for sharing any type of image, where it improves security using the Lorenz chaotic system as the source of randomness and the generalized Arnold transform as a permutation module. The second SIS system further enhances security and robustness by utilizing SHA-256 and RSA cryptosystem. The presented architectures are implemented on a field programmable gate array (FPGA) to enhance computational efficiency and facilitate real-time processing. Detailed experimental results and comparisons between the software and hardware realizations are presented. Security analysis and comparisons with related literature are also introduced with good results, including statistical tests, differential attack measures, robustness tests against noise and crop attacks, key sensitivity tests, and performance analysis. © The Author(s) 2024.
On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA
This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard 256times 256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out. © 2013 IEEE.
An inductorless CMOS realization of Chua’s circuit
In this paper, an inductorless CMOS realization of Chua’s circuit [IEEE Trans. Circ. Syst. – I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua’s circuit and can generate Rossler or double-scroll attractors by changing a single capacitor’s value. Variables are represented in the current domain to facilitate adding or subtracting variables. New Gm-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as ±1.5 V. Transistor-level simulation results using PSpice in 0.5 ?m Mietec process are presented. © 2003 Published by Elsevier Science Ltd.
MOS realization of the conjectured simplest chaotic equation
This paper presents a general block diagram of a third-order linear differential equation using current mode techniques. The realization of the conjectured simplest chaotic equation of Elwakil and Kennedy based on G m – C technology is given. The metal oxide semiconductor circuit is composed of 20 transistors and three grounded capacitors, can operate from a supply voltage as low as ± 1.5 V, and covers a very wide range of frequencies. PSpice simulation results using 0.5 ?m Mietec technology are given. A numerical solution is also included to verify the circuit operation.
MOS realization of the double-scroll-like chaotic equation
This brief presents a new chaotic circuit based on Gm-C integrators. The circuit realizes the double-scroll-like chaotic equation presented in [1], [2]. The mentioned equation describes double-scroll dynamics with a simple mathematical model. The proposed circuit uses a current-mode technique that is suitable for integrated circuit implementation and high-frequency operation using low supply voltage. A general block diagram is presented based on Gm-C integrators. Its realization using MOS transistors and three grounded capacitors is also given. Simulation results to demonstrate the practicality of the circuit are included.
On some generalized discrete logistic maps
Recently, conventional logistic maps have been used in different vital applications like modeling and security. However, unfortunately the conventional logistic maps can tolerate only one changeable parameter. In this paper, three different generalized logistic maps are introduced with arbitrary powers which can be reduced to the conventional logistic map. The added parameter (arbitrary power) increases the degree of freedom of each map and gives us a versatile response that can fit many applications. Therefore, the conventional logistic map is considered only a special case from each proposed map. This new parameter increases the flexibility of the system, and illustrates the performance of the conventional system within any required neighborhood. Many cases will be illustrated showing the effect of the arbitrary power and the equation parameter on the number of equilibrium points, their locations, stability conditions, and bifurcation diagrams up to the chaotic behavior. © 2012.
Hardware stream cipher with controllable chaos generator for colour image encryption
This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.
Crystal violet removal using algae-based activated carbon and its composites with bimetallic Fe0-Cu
The textile industry is considered a source of pollution because of the discharge of dye wastewater. The dye wastewater effluent has a significant impact on the aquatic environment. According to the World Bank, textile dyeing, and treatment contribute 17 to 20% of the pollution of water. This paper aims to prepare the bimetallic nano zero-valent iron-copper (Fe0-Cu), algae-activated carbon, and their composites (AC-Fe0-Cu), which are employed as adsorbents. In this paper, Synthetic adsorbents are prepared and examined for the adsorption and removal of soluble cationic crystal violet (CV) dye. The influence of synthetic adsorbents on the adsorption and removal of soluble cationic crystal violet (CV) dye is investigated using UV-V spectroscopy at different pH (3-10), time intervals (15-180) min, and initial dye concentrations (50-500 ppm). Raw algae exhibit an impressive 96.64% removal efficiency under the following conditions: pH 7, contact time of 180 min, rotational speed of 120 rpm, temperature range of 25 °C-30 °C, concentration of 300 ppm in the CV dye solution, and a dose of 4 g l?1 of raw algae adsorbent. The best removal efficiencies of Raw algae Fe0-Cu, and H3PO4 chemical AC-Fe0-Cu are 97.61 % and 97.46 %, respectively, at pH = 7, contact time = 150 min, rotational speed = 120 rpm, T = (25-30) °C, concentration = 75 ppm of CV dye solution, and 1.5 g l?1 doses of raw algae F e0-Cu adsorbent and 1 g l?1 dose of H3PO4 chemical AC-Fe0-Cu adsorbent. The maximum amounts (q max) of Bi-RA and RA adsorbed for the adsorption process of CV are 85.92 mg g?1 and 1388 mg g?1, respectively. The Bi-H3A-AC model, optimized using PSO, demonstrates superior performance, with the highest adsorption capacity estimated at 83.51 mg g?1. However, the Langmuir model predicts a maximum adsorption capacity (q e ) of 275.6 mg g?1 for the CV adsorption process when utilizing Bi-H3A-AC. Kinetic and isothermal models are used to fit the data of time and concentration experiments. DLS, zeta potential, FT-IR, XRD, and SEM are used to characterize the prepared materials. Response surface methodology (RSM) is used to model the removal efficiency and then turned into a numerical optimization approach to determine the ideal conditions for improving removal efficiency. An artificial neural network (ANN) is also used to model the removal efficiency. © 2024 The Author(s). Published by IOP Publishing Ltd.
Chaotic neural network quantization and its robustness against adversarial attacks
Achieving robustness against adversarial attacks while maintaining high accuracy remains a critical challenge in neural networks. Parameter quantization is one of the main approaches used to compress deep neural networks to have less inference time and less storage memory size. However, quantization causes severe degradation in accuracy and consequently in model robustness. This work investigates the efficacy of stochastic quantization to enhance robustness and accuracy. Noise injection during quantization is explored to understand the impact of noise types and magnitudes on model performance. A comprehensive comparison between different applying scenarios for stochastic quantization and different noise types and magnitudes was implemented in this paper. Compared to the baseline deterministic quantization, chaotic quantization achieves a comparable accuracy, however, it achieves up to a 43% increase in accuracy against various attack scenarios. This highlights stochastic quantization as a promising defense mechanism. In addition, there is a crucial role played by the choice of noise type and magnitude in stochastic quantization. Lorenz and Henon noise distributions in stochastic quantization outperform traditional uniform and Gaussian noise in defending against attacks. A transferability analysis was discussed to understand the generalizability and effectiveness of the proposed stochastic quantization techniques. A cross-validation definition was newly evaluated in this scope to analyse the model’s stability and robustness against attacks. The study outperformed a quantization network technique and improved the model’s robustness and stability against adversarial attacks using chaotic quantization instead of deterministic quantization or even instead of stochastic quantization using traditional noise. © 2024 Elsevier B.V.