This paper proposes a speech encryption scheme based on a generalized modified chaotic tent map and bit permutation and presents its hardware realization
FPGA implementation of fractional-order Chua’s chaotic system
2018Abdelhamed M.A.Abu-Elyazeed M.F.Confrence PaperEl-Kader A.A.A.El-Maksoud A.J.A.Hassan B.G.Radwan A.G.Rihan N.G.Said L.A.Tolba M.F.
This paper introduces FPGA implementation of fractional order double scrolls chaotic system based on Chua circuit
Generic Hardware of Fractional Order Multi-Scrolls Chaotic Generator Based on FPGA
Exploring the implementation of fractional calculus is essential to be adequately used in several applications
Generic FPGA Design of Spiking Neuron Model
This paper introduces a new representation of the human brain neuron cell response
FPGA implementation of fractional-order integrator and differentiator based on Grünwald Letnikov’s definition
The fractional-order derivative and integral of Grünwald Letnikov’s definition are implemented based on FPGA for different fractional orders
Speech encryption using generalized modified chaotic logistic and tent maps
This paper presents a speech encryption application, which utilizes several proposed generalized modified discrete chaotic maps based on the logistic and tent maps for pseudo-random number generation
FPGA Implementation of Fractional-Order Chaotic Systems
This chapter introduces two FPGA implementations of the fractional-order operators: the Caputo and the Grünwald-Letnikov (GL) derivatives. First, the Caputo derivative is realized using nonuniform segmentation to reduce the size of the Look-Up Table. The Caputo implementation introduced can generate derivatives of previously defined functions only. Generic and complete hardware architecture of the GL operator is realized with different memory window sizes. The generic architecture is used as a block to implement several fractional-order chaotic systems. The investigated systems include Borah, Chen, Liu, Li, and Arneodo fractional-order chaotic systems. Different interesting attractors are realized under various parametric changes with distinct step sizes for different fractional orders. To verify the chaotic behavior of the generated attractors, the Maximum Lyapunov Exponent is calculated for each system at different parameter values. © 2018 Elsevier Inc. All rights reserved.
FPGA implementation of integer/fractional chaotic systems
2020Abd El-Kader A.A.Abd El-Maksoud A.J.Abu-Elyazeed M.F.Book ChapterHassan B.G.Radwan A.G.Rihan N.G.Said L.A.Tolba M.F.
Chaotic systems have remarkable importance in capturing some complex features of the physical process. Recently, fractional calculus becomes a vigorous tool in characterizing the dynamics of complex systems. The fractional-order chaotic systems increase the chaotic behavior in new dimensions and add extra degrees of freedom, which increase system controllability. In this chapter, FPGA implementation of different integer and fractional-order chaotic systems is presented. The investigated integer-order systems include Chua double scroll chaotic system and the modified Chua N-scroll chaotic system. The investigated fractional-order systems include Chua, Yalcin et al., Ozuogos et al., and Tang et al., chaotic systems. These systems are implemented and simulated based on the Grunwald–Letnikov (GL) definition with different window sizes. The parameters effect, along with different GL window sizes is investigated where some interesting chaotic behaviors are obtained. The proposed FPGA implementation utilizes fewer resources and has high throughput. Experimental results are provided on a digital oscilloscope. © Springer Nature Switzerland AG 2020.
A study of the nonlinear dynamics of human behavior and its digital hardware implementation
This paper introduces an intensive discussion for the dynamical model of the love triangle in both integer and fractional-order domains. Three different types of nonlinearities soft, hard, and mixed between soft and hard, are used in this study. MATLAB numerical simulations for the different three categories are presented. Also, a discussion for how the kind of personalities affects the behavior of chaotic attractors is introduced. This paper suggests some explanations for the complex love relationships depending on the impact of memory (IoM) principle. Lyapunov exponents, Kaplan-Yorke dimension, and bifurcation diagrams for three different integer-order cases show a significant dependency on system parameters. Hardware digital realization of the system is done using the Xilinx Artix-7 XC7A100T FPGA kit. Version 14.7 from the Xilinx ISE platform is used in both Verilog simulation and hardware implementation stages. The digital approach of such a system opens the door to predict the love relation after sensing the human personality. Also, this study will help in justifying more human emotions like happiness, panic, and fear accurately. Perhaps shortly, this study may combine with artificial intelligence to demonstrate Human-Computer interaction products. © 2020
Hardware realization of a secure and enhanced s-box based speech encryption engine
This paper presents a secure and efficient substitution box (s-box) for speech encryption applications. The proposed s-box data changes every clock cycle to swap the input signal with different data, where it generated based on a new algorithm and a memristor chaotic system. Bifurcation diagrams for all memristor chaotic system parameters are introduced to stand for the chaotic range of each parameter. Moreover, the effect of each component inside the proposed encryption system is studied, and the security of the system is validated through perceptual and statistical tests. The size of the encryption key is 175 bits to meet the global standards for the optimum encryption key width (> 128). MATLAB software is used to calculate entropy, MSE, and correlation coefficient. Both chaotic circuit and encryption/decryption schemes are designed using Verilog HDL and simulated by Xilinx ISE 14.7. Xilinx Virtex 5 FPGA kit is used to realize the proposed algorithm with a throughput 0.536 of Gbit/s. The cryptosystem is tested using two different speech files to examine its efficiency. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.