This paper introduces a study to generalize the design of a continuous time filters into the fractional order domain. The study involves inverting and non-inverting filters based on CFOA where three responses are extracted which are high-pass, band-pass and low-pass responses. The proposed study introduces the generalized formulas for the transfer function of each response with different fractional orders. The fractional-order filters enhance the design flexibility and controllability due to the extra degree of freedom provided by the fractional order parameters. The general fundamentals of these filters are presented by calculating the cutoff frequency equation. Different numerical solutions for the generalized fractional order filters are introduced. Stability discussion is presented for different fractional order cases. Spice simulations results are introduced to validate the theoretical findings. © 2016 IEEE.
Fractional-order oscillator based on single CCII
This paper presents a generalization of well-known phase shift oscillator based on single CCII into the fractional order domain. The general state matrix, characteristic equation and design equations are presented. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are introduced in terms of the fractional order parameters. These parameters add extra degrees of freedom which in turn increase the design flexibility and controllability. Numerical discussion of five special cases is investigated including the integer case. Spice simulations and experimental results are introduced to validate the theoretical findings with stability discussion. © 2016 IEEE.
A Simple BJT Inverse Memristor Emulator and Its Application in Chaotic Oscillators
A generalized inverse memristor emulator is proposed based on two BJT transistors as a diode connected with a first order parallel RC filter. The mathematical model of the circuit is presented where the pinched hysteresis loops (PHLs) with different periodic stimuli are analyzed. The numerical, P-Spice simulations and experimental results are presented indicating that the introduced emulator is a simple voltage-controlled generalized inverse memristor. The results show that the PHLs area is increased with increasing the applied frequency. In addition, the proposed emulator is employed in a simple chaotic circuit. The effect of the inductor’s values on the chaotic system is investigated and the P-Spice simulations are performed to approve the numerical results. © 2019 IEEE.
Built-in-current-sensor for testing short and open faults in CMOS digital circuits
In this paper, a novel built-in sensor (BIS) for digital CMOS circuit testing has been proposed. The proposed BIS has no voltage degradation and it is able to detect, identify and localize both open and short circuit faults. Moreover, it has a simple realization with very small area and detection time. A 4×4 multiplier cell is tested by the proposed BIS and all injected faults are detected. © 2009 IEEE.
Analog fault diagnosis by inverse problem technique
A novel algorithm for detecting soft faults in linear analog circuits based on the inverse problem concept is proposed. The proposed approach utilizes optimization techniques with the aid of sensitivity analysis. The main contribution of this work is to apply the inverse problem technique to estimate the actual parameter values of the tested circuit and so, to detect and diagnose single fault in analog circuits. The validation of the algorithm is illustrated through applying it to Sallen-Key second order band pass filter and the results show that the detecting percentage efficiency was 100% and also, the maximum error percentage of estimating the parameter values is 0.7%. This technique can be applied to any other linear circuit and it also can be extended to be applied to non-linear circuits. © 2011 IEEE.
Image encryption based on double-humped and delayed logistic maps for biomedical applications
This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the one dimensional double humped logistic map as well as the two-dimensional delayed logistic map. Different analyses are introduced to measure the performance of the proposed encryption system such as: histogram analysis, correlation coefficients, MAE, NPCR as well as UACI measurements. The encryption system is proven to be highly sensitive to ±0.001% perturbation of the logistic maps parameters. The system is tested on medical images of palm print as well as Parkinson disease MRI images. © 2017 IEEE.
Two-port oscillators based on three impedance structure
This paper investigates the general analysis of the three impedance common B oscillators based on two port network. The concept is applied for 12 different impedance structures to obtain a second order oscillator where the condition and the frequency of oscillation are studied for each case. Then three special cases of two-port networks whose transmission matrices contain two non-zero elements are studied which represent MOS, BJT and gyrator circuits where six cases only can be adapted to have oscillation using gyrators. The effect on non-idealities of the current conveyor used to build gyrator on the condition and the frequency of oscillation is also studied. Finally three different cases are validated using the circuit simulations which match the theoretical study. © 2014 IEEE.
Hardware Speech Encryption Using a Chaotic Generator, Dynamic Shift and Bit Permutation
This paper proposes a speech encryption and decryption system, its hardware architecture design and FPGA implementation. The system utilizes Nosé Hoover chaotic generator and/or dynamic shift and bit permutation. The effect of different blocks in the proposed encryption scheme is studied and the security of the system is validated through perceptual and statistical tests. The complete encryption scheme is simulated using Xilinx ISE 14.5 and realized on FPGA Xilinx Kintex 7, presenting the experimental results on the oscilloscope. The efficiency is also validated through hardware resources utilization compared to previous works based on maximum frequency and throughput. © 2018 IEEE.
Generalized delayed logistic map suitable for pseudo-random number generation
This paper presents the generalization of a delayed version of the logistic map. The effect of the added two general parameters is studied, which offers the option of having three different maps. The dynamic behavior of the vertical, zooming and the general map is analyzed. The study of the fixed points, stability ranges and bifurcation diagram of the delayed logistic map at hand is detailed in this work. The flow of the system behavior from stability to chaos is also presented with its transient response as well as its phase plane portraits. Moreover, using the general parameters, the option of designing any specific map is validated by some design examples, which makes it more optimal for any specific applications. The added general parameters offer increased randomness with controllability of the map design, making it more suitable for pseudo-random sequence generators which are used in image encryption algorithms and in secure communication transfer. © 2015 IEEE.
Generalized fractional logistic map suitable for data encryption
This paper presents the generalization of a delayed version of the logistic map