Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels. © 2022 by the authors. Licensee MDPI, Basel, Switzerland.
CNTFET-based ternary address decoder design
With the end of Moore’s law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power- and time-consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre-decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs. © 2022 John Wiley & Sons Ltd.
Ternary SRAM circuit designs with CNTFETs
Static random-access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. © 2023 John Wiley & Sons Ltd.
Fractional-order Memristor Response Under DC and Periodic Signals
Recently, there is an essential demand to extend the fundamentals of the conventional circuit theory to include the new generalized elements, fractional-order elements, and mem-elements due to their unique properties. This paper presents the relationships between seven different elements based on the four physical quantities and the fractional-order derivatives. One of them is the Fractional-order memristor, where the memristor dynamic is expressed by fractional-order derivative. This element merge the memristive and fractional-order concepts together where the conventional modeling becomes a special case. Moreover, the mathematical modeling of the fractional-order memristor is introduced. In addition, the response of applying DC, sinusoidal, and nonsinusoidal periodic signals is discussed. Finally, different numerical simulations are presented. © 2014, Springer Science+Business Media New York.
Emulation circuits of fractional-order memelements with multiple pinched points and their applications
This paper proposes voltage- and current-controlled universal memelements emulators. They are employed to realize the floating and grounded fractional-order memelements. The proposed emulators are implemented using different active blocks such as the second-generation current conveyor (CCII), Differential input double output transconductance amplifier (DOTA + ), balanced output CCII, and Differential voltage current conveyor (DVCC) with analog voltage multiplier. One of the main characteristics of the memristive elements is hysteresis loop behaviour with one pinched point, and the higher-order memelements have multiple pinched points. The higher fractional-order memductance (FOM) and inverse memductance (FOIM) emulators are proposed, which achieve multiple pinched-off points. The coordinates of the multiple pinched-off points and the conditions to achieve them are discussed in the I-V plane. Additionally, the effect of different orders ? of the fractional-order capacitor (FOC) on the memelements characteristic is discussed. The circuit simulations for the proposed emulators have been verified using PSPICE simulations and validated experimentally at different orders. Finally, the grounded proposed emulator is employed in Chua’s chaotic oscillator as an application presenting the effect of fractional-order on the chaotic response. Also, the floating proposed emulator is applied to a relaxation oscillator, to show the reliability of the proposed emulator. © 2020
Simple floating voltage-controlled memductor emulator for analog applications
The topic of memristive circuits is a novel topic in circuit theory that has become of great importance due to its unique behavior which is useful in different applications. But since there is a lack of memristor samples, a memristor emulator is used instead of a solid state memristor. In this paper, a new simple floating voltage-controlled memductor emulator is introduced which is implemented using commercial off the shelf (COTS) realization. The mathematical modeling of the proposed circuit is derived to match the theoretical model. The proposed circuit is tested experimentally using different excitation signals such as sinusoidal, square, and triangular waves showing an excellent matching with previously reported simulations.
Boundary Dynamics of Memcapacitor in Voltage-Excited Circuits and Relaxation Oscillators
This paper discusses the boundary dynamics of the charge-controlled memcapacitor for Joglekar’s window function that describes the nonlinearities of the memcapacitor’s boundaries. A closed form solution for the memcapacitance is introduced for general doping factor (Formula presented.)p. The derived formulas are used to predict the behavior of the memcapacitor under different voltage excitation sources showing a great matching with the circuit simulations. The effect of the doping factor (Formula presented.) on the time domain response of the memcapacitor has been studied as compared to the linear model using the proposed formulas. Moreover, the generalized fundamentals such as the saturation time of the memcapacitor are introduced, which play an important role in many control applications. Then the boundary dynamics under sinusoidal excitation are used as a basis to analyze any periodic signal by Fourier series, and the results have been verified using PSPICE simulations showing a great matching. As an application, two configuration of resistive-less memcapacitor-based relaxation oscillators are proposed and closed form expressions for oscillation frequency and conditions for oscillation are derived in presence of nonlinear model. The proposed oscillator is verified using PSPICE simulation showing a perfect matching. © 2015, Springer Science+Business Media New York.
Resistive-less memcapacitor-based relaxation oscillator
Recently, the realization of the conventional relaxation oscillators was introduced based on memristors. This paper validates the concept using two series memcapacitors in general which is applicable for a capacitor and memcapacitor as well. Furthermore, the necessary conditions for oscillation are introduced, and a generalized closed-form expression for the oscillation frequency is derived. Two special cases are introduced and verified using PSPICE simulations showing a perfect matching. Copyright © 2014 John Wiley & Sons, Ltd.
Memcapacitor response under step and sinusoidal voltage excitations
Recently, mem-elements have become fundamental in the circuit theory through promising potential applications based on the built-in memory-properties of these elements. In this paper, the mathematical analysis of the memcapacitor model is derived and the effect of different voltage excitation signals is studied for the linear dopant model. General closed form expressions and analyses are presented to describe the memcapacitor behavior under DC step and sinusoidal voltage excitations. Furthermore, the step and sinusoidal responses are used to analyze the memcapacitor response under any periodic signal using Fourier series expansion where the effect of the DC component on the output response is investigated. In addition, the stored energy in the memcapacitor under step, sinusoidal and square wave excitations is discussed. Moreover, the analysis of series and parallel connection of N non-matched memcapacitors in general is introduced and special cases of matched memcapacitors are discussed. The derived equations are verified using SPICE simulations showing great matching. © 2014 Elsevier Ltd. All rights reserved.
Hardware realization of a secure and enhanced s-box based speech encryption engine
This paper presents a secure and efficient substitution box (s-box) for speech encryption applications. The proposed s-box data changes every clock cycle to swap the input signal with different data, where it generated based on a new algorithm and a memristor chaotic system. Bifurcation diagrams for all memristor chaotic system parameters are introduced to stand for the chaotic range of each parameter. Moreover, the effect of each component inside the proposed encryption system is studied, and the security of the system is validated through perceptual and statistical tests. The size of the encryption key is 175 bits to meet the global standards for the optimum encryption key width (> 128). MATLAB software is used to calculate entropy, MSE, and correlation coefficient. Both chaotic circuit and encryption/decryption schemes are designed using Verilog HDL and simulated by Xilinx ISE 14.7. Xilinx Virtex 5 FPGA kit is used to realize the proposed algorithm with a throughput 0.536 of Gbit/s. The cryptosystem is tested using two different speech files to examine its efficiency. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.