Artificial Neural Networks (ANNs) are remarkably able to fit complex functions, making them useful in various applications and systems. This paper uses ANN to fit the Pehlivan–Uyaroglu Chaotic System (PUCS) to produce an Artificial Neural Network Chaotic Pseudo-Random Number Generator (ANNC-PRNG). The proposed PRNG imitates the PUCS chaotic system’s properties and attractor shape. The proposed ANNC-PRNG is implemented in a simple image encryption system on the Xilinx Kintex-7 Genesys 2 Field Programmable Gate Array (FPGA) board. Hardware realization of an ANN trained on chaotic time series has not been presented before. The proposed ANN can be used for different numerical methods or chaotic systems, including fractional-order systems while keeping the same resources despite the methodsÂ’ complexity or chaotic systemsÂ’ complexity. Extensive testing for the ANNC-PRNG was done to prove the randomness of the produced outputs. The proposed ANNC-PRNG and the encryption system passed various well-established security and statistical tests and produced good results compared to recent similar research. The encryption system is robust against different attacks. The proposed hardware architecture is fast as it reaches a maximum frequency of 12.553 MHz throughput of 301 Mbit/s. © 2023 Elsevier Ltd
An Efficient Multi-Secret Image Sharing System Based on Chinese Remainder Theorem and Its FPGA Realization
Multi-Secret Image Sharing (MSIS) is important in information security when multiple images are shared in an unintelligible form to different participants, where the images can only be recovered using the shares from participants. This paper proposes a simple and efficient ( n,n )-MSIS system for colored images based on XOR and Chinese Remainder Theorem (CRT), where all the n share are required in the recovery. The system improves the security by adding dependency on the input images to be robust against differential attacks, and by using several delay units. It works with even and odd number of inputs, and has a long sensitive system key design for the CRT. Security analysis and a comparison with related literature are introduced with good results including statistical tests, differential attack measures, and key sensitivity tests as well as performance analysis tests such as time and space complexity. In addition, Field Programmable Gate Array (FPGA) realization of the proposed system is presented with throughput 530 Mbits/sec. Finally, the proposed MSIS system is validated through software and hardware with all statistical analyses and proper hardware resources with low power consumption, high throughput and high level of security. © 2013 IEEE.
CNTFET-Based Ternary Multiply-and-Accumulate Unit
Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels. © 2022 by the authors. Licensee MDPI, Basel, Switzerland.
CNTFET-based ternary address decoder design
With the end of Moore’s law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power- and time-consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre-decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs. © 2022 John Wiley & Sons Ltd.
Ternary SRAM circuit designs with CNTFETs
Static random-access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. © 2023 John Wiley & Sons Ltd.
FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System with Transcendental Nonlinearities
Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC. © 2004-2012 IEEE.
Active and passive sensitivity analysis for the second-order active RC filter families using operational amplifier: a review
This work is a review article that sheds light on the active and passive sensitivities of the active RC filters based on opamp. This work provides a detailed analysis through different filters realization criteria and sensitivity summary tables and quantitative insight by discussing the most significant. However, some are almost forgotten, filters families in the literature over decades. A detailed mathematical analysis for the passive sensitivity to compare the filters’ realizations is presented. The concept of dealing between filter design theory and filter design circuit realization is highlighted. Some filters families are chosen from the literature for the analysis. Some detailed specifications tables for each filter family are given. Monte Carlo simulation is carried out on some filters to compare their passive sensitivity. Furthermore, the effect of the active sensitivity of some filters is verified through simulation by adjusting the input common-mode voltage to lower the DC gain of the amplifier. The results of the simulation match with the theoretical analysis and the summary provided in the specifications tables. © 2022, The Author(s).
On the Design Flow of the Fractional-Order Analog Filters Between FPAA Implementation and Circuit Realization
This work explicitly states the design flows of the fractional-order analog filters used by researchers throughout the literature. Two main flows are studied: the FPAA implementation and the circuit realization. Partial-fraction expansion representation is used to prepare the approximated fractional-order response for implementation on FPAA. The generalization of the second-order active RC analog filters based on opamp from the integer-order domain to the fractional-order domain is presented. The generalization is studied from both mathematical and circuit realization points of view. It is found that the great benefit of the fractional-order domain is that it adds more degrees of freedom to the filter design process. Simulation and experimental results match the expected theoretical analysis. © 2013 IEEE.
A Unified FPGA Realization for Fractional-Order Integrator and Differentiator
This paper proposes a generic FPGA realization of an IP core for fractional-order integration and differentiation based on the Grünwald–Letnikov approximation. All fractional-order dependent terms are approximated to simpler relations using curve fitting to enable an efficient hardware realization. Compared to previous works, the proposed design introduces enhancements in the fractional-order range covering both integration and differentiation. An error analysis between software and hardware results is presented for sine, triangle and sawtooth signals. The proposed generic design is realized on XC7A100T FPGA achieving frequency of 9.328 MHz and validated experimentally for a sine input signal on the oscilloscope. The proposed unified generic design is suitable for biomedical signal processing applications. In addition, it can be employed as a laboratory tool for fractional calculus education. © 2022 by the authors. Licensee MDPI, Basel, Switzerland.
CORDIC-Based FPGA Realization of a Spatially Rotating Translational Fractional-Order Multi-Scroll Grid Chaotic System
This paper proposes an algorithm and hardware realization of generalized chaotic systems using fractional calculus and rotation algorithms. Enhanced chaotic properties, flexibility, and controllability are achieved using fractional orders, a multi-scroll grid, a dynamic rotation angle(s) in two- and three-dimensional space, and translational parameters. The rotated system is successfully utilized as a Pseudo-Random Number Generator (PRNG) in an image encryption scheme. It preserves the chaotic dynamics and exhibits continuous chaotic behavior for all values of the rotation angle. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used to implement rotation and the Grünwald–Letnikov (GL) technique is used for solving the fractional-order system. CORDIC enables complete control and dynamic spatial rotation by providing real-time computation of the sine and cosine functions. The proposed hardware architectures are realized on a Field-Programmable Gate Array (FPGA) using the Xilinx ISE 14.7 on Artix 7 XC7A100T kit. The Intellectual-Property (IP)-core-based implementation generates sine and cosine functions with a one-clock-cycle latency and provides a generic framework for rotating any chaotic system given its system of differential equations. The achieved throughputs are (Formula presented.) Mbits/s and (Formula presented.) Mbits/s for two- and three-dimensional rotating chaotic systems, respectively. Because it is amenable to digital realization, the proposed spatially rotating translational fractional-order multi-scroll grid chaotic system can fit various secure communication and motion control applications. © 2022 by the authors.